Patents by Inventor Jen-Chi Chuang
Jen-Chi Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120068147Abstract: A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.Type: ApplicationFiled: November 23, 2011Publication date: March 22, 2012Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Jen-Chi CHUANG, Ming-Jeng HUANG, Chien-Min LEE, Jia-Yo LIN, Min-Chih WANG
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Publication number: 20110312150Abstract: A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Chien-Min Lee, Ming-Jeng Huang, Jen-Chi Chuang, Jia-Yo Lin, Min-Chih Wang
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Patent number: 7858961Abstract: An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively.Type: GrantFiled: November 28, 2008Date of Patent: December 28, 2010Assignee: Industrial Technology Research InstituteInventors: Jen-Chi Chuang, Yung-Fa Lin, Ming-Jeng Huang
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Publication number: 20100213432Abstract: A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.Type: ApplicationFiled: May 19, 2009Publication date: August 26, 2010Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Jen-Chi Chuang, Ming-Jeng Huang, Chien-Min Lee, Jia-Yo Lin, Min-Chih Wang
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Publication number: 20100133495Abstract: A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.Type: ApplicationFiled: September 2, 2009Publication date: June 3, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Chien-Min Lee, Ming-Jeng Huang, Jen-Chi Chuang, Jia-Yo Lin, Min-Chih Wang
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Publication number: 20090294750Abstract: An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively.Type: ApplicationFiled: November 28, 2008Publication date: December 3, 2009Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Jen-Chi Chuang, Yung-Fa Lin, Ming-Jeng Huang
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Publication number: 20090161406Abstract: A non-volatile memory including a diode and a memory cell is described. The diode includes a doped region, a metal silicide layer, and a patterned doped semiconductor layer. The doped region of a first conductive type is formed in a substrate. The metal silicide layer is formed on the substrate. The patterned doped semiconductor layer of a second conductive type is formed on the metal silicide layer. The memory cell is formed on the substrate and coupled with the diode.Type: ApplicationFiled: March 25, 2008Publication date: June 25, 2009Applicant: Powerchip Semiconductor Corp.Inventors: Jen-Chi Chuang, Chiu-Tsung Huang, Yu-Chieh Liao
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Publication number: 20080011230Abstract: Chemical vapor deposition equipment includes a reactor, an adjustable pipe, and an exhausted pipe. The adjustable pipe includes a compressible body, a bushing, and a ring positioned at an end of the body for connecting with the exhausted pipe. The bushing is positioned inside the body, and an end of the bushing is connected to the reactor for preventing exhaust gas from remaining inside the body. In addition, the compressible body is monolithically formed. Therefore, exhaust gas will not leak from the body, which improves the quality of manufacture.Type: ApplicationFiled: May 11, 2006Publication date: January 17, 2008Inventors: Chih-Wei Ke, Jen-Chi Chuang, Shih-Heng Fan
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Patent number: 7183158Abstract: A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer, charge trapping layer and bottom dielectric layer are removed to form several trenches. An insulation layer is formed in the trenches to form a plurality of isolation structures. A plurality of word lines are formed on the conductive layer and the isolation structures. By using the word lines as a mask, portions of bottom dielectric layer, charge trapping layer, top dielectric layer, conductive layer and isolation structures are removed to form a plurality of devices. The bottom oxide layer has different thickness on the substrate so that these devices can be provided with different performance. These devices serve as memory cells with different character or devices in periphery region.Type: GrantFiled: June 8, 2005Date of Patent: February 27, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Chien-Lung Chu, Jen-Chi Chuang
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Publication number: 20060063329Abstract: A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer, charge trapping layer and bottom dielectric layer are removed to form several trenches. An insulation layer is formed in the trenches to form a plurality of isolation structures. A plurality of word lines are formed on the conductive layer and the isolation structures. By using the word lines as a mask, portions of bottom dielectric layer, charge trapping layer, top dielectric layer, conductive layer and isolation structures are removed to form a plurality of devices. The bottom oxide layer has different thickness on the substrate so that these devices can be provided with different performance. These devices serve as memory cells with different character or devices in periphery region.Type: ApplicationFiled: June 8, 2005Publication date: March 23, 2006Inventors: Chien-Lung Chu, Jen-Chi Chuang