Abstract: An electronic paper touch device including: a first substrate; a first electrode layer located on the first substrate; an electronic paper display layer located on the first electrode layer; a transparent electrode layer located on the electronic paper display layer and having plural transparent electrodes; a second substrate located on the transparent electrode layer; and a control unit having a touch mode and an electronic paper mode, wherein, when the control unit is in the touch mode, the control unit will couple a touch detection unit with the first electrode layer and with the transparent electrode layer to perform a capacitive touch detection procedure.

Abstract: A touch display having advanced-fringe-field-switching liquid crystal structure, including a pixel cell and a multiplexer circuit, wherein the multiplexer circuit is used to couple the pixel cell with a source driver unit to provide a fringe-field-switching display function during a display period, and couple the pixel cell with a touch detection unit to provide a touch detection function during a touch detection period.

Abstract: A touch display having in-plane-switching liquid crystal structure, comprising a pixel cell and a multiplexer circuit, wherein the multiplexer circuit is used to couple a source driver unit with the pixel cell to provide an in-plane switching display function during a display period, and couple a touch control unit with the pixel cell to provide a touch detection function during a touch detection period.

Abstract: A touch display driving circuit capable of responding to CPU commands, including: a first interface for receiving pixel data and touch configuration data; a second interface for coupling with a touch display; and a control unit, which drives the touch display via the second interface to show an image according to the pixel data, and executes a touch detection procedure on the touch display via the second interface, wherein the touch detection procedure is determined according to the touch configuration data.

Abstract: A control method for bidirectional DC-DC converter includes: operating a bidirectional DC-DC converter in a boost mode, the bidirectional DC-DC converter including a low voltage side and a high voltage side, the low voltage side including low-voltage-side switches, a voltage clamping switch and a voltage clamping capacitor and the high voltage side including high-voltage-side switches; switching the voltage clamping switch with a predetermined duty cycle prior to switching on all of the low-voltage-side switches; adjusting the duty cycle of the voltage clamping switch being smaller than a turn-off interval of the low-voltage-side switches to reduce the conduction loss of the low-voltage-side switches and the voltage clamping switch; alternatively, operating the DC-DC converter in a buck mode; adjusting and extending the duty cycle of the low-voltage-side switches to overlap a turn-off time of the high-voltage-side switches so as to reduce the conduction loss of the low-voltage-side switches.

Abstract: A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C., and forming a doped amorphous silicon layer in a upper portion of the amorphous silicon layer at a reaction temperature between about 520° C. and 560° C.

Abstract: A motor magnetic pre-stressing apparatus includes a stator and a rotor. The rotor is pivoted with the stator. The stator includes a lower insulating frame and a magnetic-guiding ring, and the magnetic-guiding ring is installed on the lower insulating frame. The rotor has a magnetic element, and the magnetic element has even radial magnetic poles. Thereby, by utilizing the attraction between magnetic-guiding ring and the magnetic element, a magnetic pre-stressing force is generated to absorb the rotor downwards so that the rotor rotates stably and smoothly.

Abstract: A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process.

Abstract: A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having a semiconductor substrate, a protective layer formed on the semiconductor substrate, and a polysilicon layer formed on the protective layer; and removing the polysilicon layer. The wafer and the reclaiming method of the wafer can prevent the substrate of the wafer from being destroyed during the reclaiming process and increase the reclaiming rate of the wafer.

Abstract: The present invention provides a three-phase motor stator. The shape of the three-phase motor stator is defined by an optimum pole-tooth ratio for reducing the cogging torque of the motor and increasing the efficiency of the motor. The three-phase motor stator includes at least one plate board. The plate board has a circular hole. A plurality of pole-teeth protrude from the rim of the circular hole and the pole-teeth are symmetric. An opening slot is individually located between two adjacent pole-teeth. The pole-tooth ratio ? defined by the tooth angle of a single pole-tooth divided by the pole pitch of two adjacent pole-teeth is between 0.65 and 0.85.

Abstract: Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semiconductor substrate; oxidizing a first part of the polysilicon layer to form a first oxide layer; removing the first oxide layer; and oxidizing a second part of the polysilicon layer to form a second oxide layer on the used wafer which is to be used as a reclaimed wafer. The nonproductive wafer is used to improve the quality of a deposition process of the polysilicon layer on one or more productive wafers.

Abstract: Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on the polysilicon layer; (d) forming and defining a photoresist layer on the poly oxide layer for exposing parts of the poly oxide layer; (e) etching the poly oxide layer, the polysilicon layer and the gate oxide layer via the photoresist layer for forming a poly oxide structure, a polysilicon structure and a gate oxide structure; and (f) removing the photoresist layer. The present invention introduces a poly oxide layer instead of the CVD oxide for preventing the photoresist lifting issue.

Abstract: A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substrate in a region not covered with the barrier layer by introducing pure dry oxygen, and performing a wet oxidation process to form a second field oxide adjacent the first field oxide by introducing hydrogen and oxygen. The method of the present invention can improve the quality and electrical property of the semiconductor device, increase the yield, and reduce the cost.

Abstract: Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.

Abstract: A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substrate in a region not covered with the barrier layer by introducing pure dry oxygen, and performing a wet oxidation process to form a second field oxide adjacent the first field oxide by introducing hydrogen and oxygen. The method of the present invention can improve the quality and electrical property of the semiconductor device, increase the yield, and reduce the cost.

Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.

Abstract: Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.

Abstract: A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process.

Abstract: Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semiconductor substrate; oxidizing a first part of the polysilicon layer to form a first oxide layer; removing the first oxide layer; and oxidizing a second part of the polysilicon layer to form a second oxide layer on the used wafer which is to be used as a reclaimed wafer. The nonproductive wafer is used to improve the quality of a deposition process of the polysilicon layer on one or more productive wafers.