Abstract: The present invention provides a method for driving a liquid crystal display panel. The liquid crystal display panel has a plurality of pixels arranged in a matrix form and a plurality of data lines. The method includes generating gray level signals corresponding to the plurality of pixels according to input image data; determining whether the gray level values of the pixels in a same row corresponding to the plurality of data lines of a first color are all outside a first range; and when the gray level values of the pixels in the same row corresponding to the plurality of data lines of the first color are all outside the first range, controlling polarity of the gray level signals of the pixels in the same row corresponding to the plurality of data lines of the first color in a column inversion mode.

Abstract: A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface.

Abstract: An exemplary image displaying method for a display device includes steps of: providing display data to pixels of the display device for displaying images; taking a special amount of frame of images as an image group, making polarities of a same pixel being of adjacent two frame of images in the image group and using a same polarity inversion in the adjacent two frame of images be different from each other, and making polarities of a same pixel being of the last frame of image in a former one of adjacent two image groups and of the first frame of image in a latter one of the adjacent two image groups and using the same polarity inversion in the last and first frame of images be the same with each other.

Abstract: A source-driving circuit comprises a plurality of first and second data-outputting units, a first and a second charge-sharing units and a charge-sharing switch circuit. The first and second data-outputting units have corresponding first and second output terminals respectively for outputting data signals with a first polarity and a second polarity. The first and second charge-sharing units comprise a plurality of first and second switches respectively. Each first switch is electrically connected between each two first output terminals and each two second output terminals. Each second switch is electrically connected between one of the first outputting terminals and a corresponding one of the second outputting terminals. A charge-sharing switch circuit is electrically connected to the first and second charge-sharing units for outputting a switch signal to the first and second charge-sharing units according to a polarity signal, so as to determine the on/off statuses of the first and second switches.

Abstract: A solar cell and a manufacturing method thereof are provided. A laser doping process is adopted to form positive and negative doping regions for an accurate control of the doping regions. No metal contact coverage issue arises since a contact opening is formed by later firing process. The solar cell is provided with a comb-like first electrode, a sheet-like second electrode corresponding to the doping regions to obtain high photoelectric conversion efficiency by fully utilizing the space in the semiconductor substrate. Furthermore, the sheet-like second electrode can be formed by a material having high reflectivity to improve the light utilization rate of the solar cell. The manufacturing process of the solar cell is simplified and the processing yield is improved.

Abstract: A solar cell includes a crystalline semiconductor substrate; a first crystalline semiconductor layer; an amorphous semiconductor layer; a first metal electrode layer and a second metal electrode layer. The crystalline semiconductor substrate has a first surface and a second surface, and the crystalline semiconductor substrate has a first doped type. The first crystalline semiconductor layer is disposed on the first surface of the crystalline semiconductor substrate, where the first crystalline semiconductor layer has a second doped type contrary to the first doped type. The amorphous semiconductor layer is disposed on the first crystalline semiconductor layer, and the amorphous semiconductor layer has the second doped type. The first metal electrode layer is disposed on the amorphous semiconductor layer. The second metal electrode layer is disposed on the second surface of the crystalline semiconductor substrate.

Abstract: A gate pulse modulating circuit includes a timing controller capable of generating an output enable signal and a plurality of timing control signals; a high gate voltage generating unit, electrically connected to the timing controller for receiving the timing control signals, capable of generating a high gate voltage with a waveform including a plurality of cutting edges in response to the timing control signals; a low gate voltage generating unit capable of generating a low gate voltage; and a gate driver, electrically connected to the timing controller for receiving the output enable signal and the high gate voltage generating unit for receiving the high gate voltage and the low gate voltage generating unit for receiving the low gate voltage, capable of generating a plurality of gate pulses in response to a plurality of enable periods of the output enable signal; wherein a waveform of the gate pulses includes a plurality of cutting edges.

Abstract: A manufacturing method for manufacturing a light-sensing structure is provided. The manufacturing method includes the steps as follows. (a) A circuit layer is formed on an upper surface of a first substrate, wherein the first substrate includes at least one light-sensing device and the circuit layer includes at least one device structure and at least one release feature that is made of metal and is formed on part of the light-sensing device and the device structure. (b) A first light-filtering layer is formed on part of the circuit layer. (c) The release feature is removed by a wet-etching process.

Abstract: An exemplary gate driving circuit is formed on a substrate and includes a plurality of shift register stages successively arranged on the substrate along a predetermined direction. The shift register stages are grouped into a plurality of groups and for outputting a plurality of gate driving signals. Each of the groups includes a plurality of cascade-connected the shift register stages. Time sequences of a plurality of start pulse signals inputted into the groups are different from one another. An output order of the gate driving signals is different from the arranging order of all the shift register stages.

Abstract: The present invention in one aspect relates to a source driver for driving a display panel to display an image data in an adaptive column inversion. In one embodiment, the source driver includes a data processing unit having a logic circuit adapted for determining N most-significant bits (MSBs) of image data signals of two neighboring data lines, such that when all of the N MSBs are equal to 1 or 0, the output of the logic circuit is 1, otherwise, the output of the logic circuit is 0, and a MUX coupled to the data processing unit and adapted for receiving a frame polarity control signal, FramePOL, and a pixel polarity control signal, XPOL, and selectively outputting the frame polarity control signal FramePOL when the output of the logic circuit is 1, or the pixel polarity control signal POL when the output of the logic circuit is 0, as a polarity control signal, POL.

Abstract: A method for driving a liquid crystal display adjusts the falling edges of the gate driving signals for reducing image flicker. A first gate driving signal falls from a high level to a first level at the signal falling edge. A second gate driving signal falls from the high level to a second level at the signal falling edge. When the parasitic capacitance of a first pixel is larger than that of a second pixel, the first level is lower than the second level; when the parasitic capacitance of the first pixel is substantially the same as that of the second pixel, the first level is the same as the second level; when the parasitic capacitance of the first pixel is smaller than that of the second pixel, the first level is higher than the second level.

Abstract: A method for centralized link power management control (CLMC), performed by a north-bridge of a processing unit, comprises the following steps. A data transmission status of a bus is monitored. CLMC is activated to configure devices corresponding to the bus in order to speed up data transmission of the bus when detecting that the data transmission status of the bus is continually busy. CLMC is activated to configure devices corresponding to the bus in order to slow down data transmission of the bus when detecting that the data transmission status of the bus is continually idle.

Abstract: A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.

Abstract: A method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset is provided. In the method, the processor first notifies the chipset of CDLC enablement. The chipset then issues a command to the processor after receiving notification of CDLC enablement. The processor broadcasts a preparation completion signal after receiving the command. The chipset asserts a signal and activates a timer to start counting after receiving the preparation completion signal. The processor configures devices of the processor, corresponding to a bus, according to one of multiple sets of first link management mode (LMM) configuration parameters in a first LMM register of the processor, indicated by first link management action field (LMAF) code in a first LMAF register of the processor, after detecting that the signal is asserted.

Abstract: A method for centralized link power management control (CLMC), performed by a north-bridge of a processing unit, comprises the following steps. A data transmission status of a bus is monitored. CLMC is activated to configure devices corresponding to the bus in order to speed up data transmission of the bus when detecting that the data transmission status of the bus is continually busy. CLMC is activated to configure devices corresponding to the bus in order to slow down data transmission of the bus when detecting that the data transmission status of the bus is continually idle.

Abstract: A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP bus. The second bridge is electrically connected between the first AGP bus and the PCI bus. The controller is electrically connected to the first AGP bus, the first bridge, and the second bridge. As a configuration cycle corresponding to the first bridge being transmitted through the first AGP bus to the controller, the controller responds a preset message implying that the first bridge does not exist.

Abstract: A method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset is provided. In the method, the processor first notifies the chipset of CDLC enablement. The chipset then issues a command to the processor after receiving notification of CDLC enablement. The processor broadcasts a preparation completion signal after receiving the command. The chipset asserts a signal and activates a timer to start counting after receiving the preparation completion signal. The processor configures devices of the processor, corresponding to a bus, according to one of multiple sets of first link management mode (LMM) configuration parameters in a first LMM register of the processor, indicated by first link management action field (LMAF) code in a first LMAF register of the processor, after detecting that the signal is asserted.

Abstract: A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.

Abstract: An extracted liquid automatic collecting equipment includes an automatic control device, an input container, a reaction column, a pump electrically connected to the automatic control device, an automatic rolling device electrically connected to the automatic control device, a plurality of collecting devices, a plurality of connecting tubes disposed between the collecting devices and the automatic rolling device. The pump is connected to the input container and the reaction column. The automatic rolling device is connected to the reaction column. The connecting tubes connect the collecting devices to the automatic rolling device.

Abstract: A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP bus. The second bridge is electrically connected between the first AGP bus and the PCI bus. The controller is electrically connected to the first AGP bus, the first bridge, and the second bridge. As a configuration cycle corresponding to the first bridge being transmitted through the first AGP bus to the controller, the controller responds a preset message implying that the first bridge does not exist.