Abstract: A computing circuit is configured to perform a bit-serial multiplication of an input signal and a weight signal. A multiplier circuit is configured to receive the input signal and the weight signal and to provide a product sum. An adder circuit is configured to receive the product sum and to provide a partial sum. A partial sum register is configured to: clock-gate a second part of the partial sum register; receive the partial sum; provide, based on the partial sum, a first output of the bit-serial multiplication through a first part of the partial sum register; determine whether not to clock-gate the second part of the partial sum register or not based on a first feature bit of the partial sum; and provide, based on the first feature bit of the partial sum, a second output of the bit-serial multiplication through the second part of the partial sum register.

Abstract: The present application discloses a light-emitting device comprises a semiconductor light-emitting element, a transparent element covering the semiconductor light-emitting element, an insulating layer which connects to the transparent element, an intermediate layer which connects to the insulating layer; and a conductive adhesive material connecting to the intermediate layer.

Abstract: Embodiment described herein provide systems, apparatuses and methods for convoluting a filter (“kernel”) to input data in the form of an input array by reusing computations of repeated data entries in the input array due to convolution movements from one convolution step to the next. In one embodiment, to compute a convolution of an input matrix and a filter matrix, instead of unrolling data entries from the input matrix of each convolution step into an input vector, only non-repeated new data entries at each convolution step may be added to the input vector. An input mapping circuit that implements an input parameter mapping matrix may then iteratively map data entries of the input vector to different weight registers that corresponds to weights in the filter matrix.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: An integrated circuit includes a memory storage having bit cells, a write path switch configured to have a connection state determined by a reliability indicator, and a write driver having an input configured to receive an input data from a write terminal through either a first write path or a second write path. The input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. The reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.

Abstract: A resistive random access memory (ReRAM) apparatus is provided. The ReRAM apparatus includes a plurality of memory cells, each of the memory cells comprises a transistor and a resistor; a bit line connected to a first terminal of the resistor of each of the memory cells; a local source line connected to a source electrode of the transistor of each of the memory cells; and a driving cell connected between the local source line and a global source line. A method for operating the ReRAM apparatus is also provided.

Abstract: A memory device includes a set of word lines, first and second sets of bit lines, a first source line having first and second source line contacts, first and second strings of transistors electrically coupled in parallel between the first and second source line contacts of the source line, and first and second sets of data storage elements. Each word line in the set of word lines is electrically coupled to gates of a transistor in the first string and a corresponding transistor in the second string. The first set of data storage elements is electrically coupled between the first string of transistors and the first set of bit lines. The second set of data storage elements is electrically coupled between the second string of transistors and the second set of bit lines.

Abstract: A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.

Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.

Abstract: A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells either as the first state or as the second state conditioning upon whether the bit value of the characterization bit is a first value or a second value. Reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.

Abstract: A memory device includes a set of word lines, a set of bit lines, a source line having first and second source line contacts, a set of transistors serially coupled between the first and second source line contacts of the source line, and a set of data storage elements. The set of transistors has gates coupled to corresponding word lines in the set of word lines. Each data storage element in the set of data storage elements is coupled between a common terminal of a corresponding pair of adjacent transistors in the set of transistors, and a corresponding bit line in the set of bit lines.

Abstract: A method of storing a data into a memory storage having bit cells. The method includes identifying each of the binary one and the binary zero in the data as either a majority bit value or a minority bit value based on the probability of finding the binary one in the data or based on the probability of finding the binary zero in the data. In the method, a bit of the data is stored into the bit cell as the more preferred state if the bit of the data has the majority bit value, and a bit of the data is stored into the bit cell as the less preferred state if the bit of the data has the minority bit value.

Abstract: A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.

Abstract: A semiconductor device includes a memory cell including a first transistor, a second transistor, and a third transistor. The first transistor has a first gate terminal and the second transistor has a second gate terminal, the first gate terminal and the second gate terminal being connected to a first word line and a second word line, respectively. The first transistor has a pair of first source/drain terminals and the second transistor has a pair of second source/drain terminals, one of the pair of first source/drain terminals and one of the pair of second source/drain terminals being connected to a common bit line. The third transistor has a third gate terminal connected to the other of the pair of first source/drain terminals, and a pair of third source/drain terminals connected to the other of the pair of second source/drain terminals and a supply voltage, respectively.

Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.

Abstract: A circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third PMOS transistor coupled between the first data line and the first input terminal, a fourth PMOS transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node, and a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.

Abstract: A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.

Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Abstract: A circuit includes a reference voltage node, first and second data lines, a sense amplifier, first and second switching devices coupled between the first and second data lines and first and second input terminals of the sense amplifier, third and fourth switching devices coupled between the first and second data lined and first and second nodes, fifth and sixth switching devices coupled between the first and second nodes and the reference voltage node, and first and second capacitive devices coupled between the first and second nodes and second and first input terminals. Each of the first through fourth switching devices is switched on and each of the fifth and sixth switching devices is switched off in a first operational mode, and each of the first through fourth switching devices is switched off and each of the fifth and sixth switching devices is switched on in a second operational mode.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.