Abstract: Embodiments of this invention provide a measurement map configuration method and apparatus. A wafer to be inspected is provided. The wafer includes a plurality of inspection marks. A first inspection result is obtained based on a first set of inspection marks. A second set of inspection marks is selected based on a preset rule. The second set of inspection marks is less than the first set of inspection marks. A second inspection result is obtained based on the second set of inspection marks. If an overlay accuracy of the second inspection result matches an overlay accuracy the first inspection result, a measurement map for the wafer is set based on target inspection marks. The target inspection marks are the second set of inspection marks of the measurement map.

Abstract: Embodiments of the present application provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a substrate; a first mask layer positioned on the substrate, wherein the first mask layer has a plurality of discrete first mask patterns; and a second mask layer positioned on the first mask layer, wherein the second mask layer has a second mask pattern, and at least a part of sidewalls of the second mask pattern is positioned on tops of the first mask patterns.

Abstract: The examples of the present application disclose a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a functional structure and a first mark structure located on a substrate, in which the functional structure and the first mark structure have the same feature size; and a first dielectric layer located at the functional structure and the first mark structure, in which a thickness of the first dielectric layer at the functional structure is different from a thickness of the first dielectric layer at the first mark structure. The examples of the present application can improve the alignment accuracy of the manufacturing process and improve the product yield and production efficiency at the same time.

Abstract: Embodiments of this invention provide a measurement map configuration method and apparatus. A wafer to be inspected is provided. The wafer includes a plurality of inspection marks. A first inspection result is obtained based on a first set of inspection marks. A second set of inspection marks is selected based on a preset rule. The second set of inspection marks is less than the first set of inspection marks. A second inspection result is obtained based on the second set of inspection marks. If an overlay accuracy of the second inspection result matches an overlay accuracy the first inspection result, a measurement map for the wafer is set based on target inspection marks. The target inspection marks are the second set of inspection marks of the measurement map.

Abstract: Embodiments of the present application provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a substrate; a first mask layer positioned on the substrate, wherein the first mask layer has a plurality of discrete first mask patterns; and a second mask layer positioned on the first mask layer, wherein the second mask layer has a second mask pattern, and at least a part of sidewalls of the second mask pattern is positioned on tops of the first mask patterns.

Abstract: The examples of the present application disclose a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a functional structure and a first mark structure located on a substrate, in which the functional structure and the first mark structure have the same feature size; and a first dielectric layer located at the functional structure and the first mark structure, in which a thickness of the first dielectric layer at the functional structure is different from a thickness of the first dielectric layer at the first mark structure. The examples of the present application can improve the alignment accuracy of the manufacturing process and improve the product yield and production efficiency at the same time.