Abstract: A memory device is provided. The memory device includes a substrate and a first stack structure. The first stack structure includes a tunneling layer. The tunneling layer includes SixOyNz, wherein x:y is 1:0.1 to 1:10, and x:z is 1:0.1 to 1:10. The first stack structure further includes a charge layer disposed over the tunneling layer and a first silicon oxide layer disposed over the charge layer. The first stack structure further includes a first gate line disposed over the first silicon oxide layer. The memory device further includes a source line doped region disposed in the substrate and disposed at the first side of the first stack structure. The memory device further includes a bit line doped region disposed in the substrate and disposed at the second side of the first stack structure. A method for manufacturing the memory device is also provided.

Abstract: A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness.

Abstract: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.

Abstract: A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness.

Abstract: A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness. Dopants are implanted for formation of source and drain regions in the second and third areas. A silicon nitride spacer material is deposited over the word lines and gates, and etched to form sidewall spacers on the gates. Dopants are implanted aligned with the sidewall spacers in the second and third areas.

Abstract: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.

Abstract: A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate oxide layer. A plurality of bit lines is formed in the substrate. A second conductive layer is then formed on the first conductive layer, followed by forming a plurality of ROM codes in the substrate.

Abstract: A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness. Dopants are implanted for formation of source and drain regions in the second and third areas. A silicon nitride spacer material is deposited over the word lines and gates, and etched to form sidewall spacers on the gates. Dopants are implanted aligned with the sidewall spacers in the second and third areas.

Abstract: A method for fabricating a y-direction, self-alignment mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a gate oxide layer on the substrate. Perpendicular to the direction of the buried drain region, a bar-shaped silicon nitride layer is formed on the gate oxide layer. A photoresist layer is then formed on the gate oxide layer and the bar-shaped silicon nitride layer. Performing a code implantation to form a plurality of coded memory cells using the photoresist layer as a mask. The photoresist layer is then removed. A polysilicon layer is further formed on the gate oxide layer and the bar-shaped silicon nitride layer. The polysilicon layer is back-etched until the bar-shaped silicon nitride layer is exposed. The silicon nitride layer is subsequently removed.

Abstract: A method for fabricating a y-direction, self-alignment mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a gate oxide layer on the substrate. Perpendicular to the direction of the buried drain region, a bar-shaped silicon nitride layer is formed on the gate oxide layer. A photoresist layer is then formed on the gate oxide layer and the bar-shaped silicon nitride layer. Performing a code implantation to form a plurality of coded memory cells using the photoresist layer as a mask. The photoresist layer is then removed. A polysilicon layer is further formed on the gate oxide layer and the bar-shaped silicon nitride layer. The polysilicon layer is back-etched until the bar-shaped silicon nitride layer is exposed. The silicon nitride layer is subsequently removed.

Abstract: A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate oxide layer. A plurality of bit lines is formed in the substrate. A second conductive layer is then formed on the first conductive layer, followed by forming a plurality of ROM codes in the substrate.

Abstract: A method for fabricating a mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a thick oxide layer on the substrate. Perpendicular to the direction of the buried drain region, a bar-shaped silicon nitride layer is formed on the thick oxide layer. A portion of the thick oxide layer is then removed to expose the substrate, followed by forming a gate oxide layer on the exposed substrate surface for forming a plurality of coded memory cells, wherein the coded memory cells with a gate oxide layer corresponds to a logic state “1” while the code memory cells with a thick silicon oxide layer corresponds to a logic state “0”. A polysilicon layer is then formed on the substrate, followed by back-etching the polysilicon layer to expose the bar-shaped silicon nitride layer. After this, the bar-shaped silicon nitride layer is removed.