Patents by Inventor Jen-Chun Liao

Jen-Chun Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087571
    Abstract: A package structure includes a carrier substrate and a die. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The semiconductor substrate is located between the conductive posts and the carrier substrate.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
  • Publication number: 20240429101
    Abstract: A method includes forming a database, finding a plurality of dicing marks on a wafer, wherein patterns of the plurality of dicing marks match a pattern in the database, measuring a die pitch of the wafer according to a patch of adjacent two of the plurality of dicing marks, and determining kerf centers of the wafer based on the plurality of dicing marks. The measuring the die pitch and the determining the kerf centers are performed on a same wafer-holding platform. The wafer is diced into a plurality of dies, and the dicing is performed aligning to the kerf centers.
    Type: Application
    Filed: October 19, 2023
    Publication date: December 26, 2024
    Inventors: Jen-Chun Liao, Chih-Wei Lin, Ching-Hua Hsieh, Wen-Chih Chiou
  • Patent number: 12176279
    Abstract: A package structure includes a carrier substrate, a die, and an encapsulant. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The conductive posts face away from the carrier substrate. The encapsulant laterally encapsulates the die.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
  • Publication number: 20240379404
    Abstract: A method for handling a semiconductor substrate includes: placing a semiconductor substrate over a semiconductor apparatus, where a central portion of the semiconductor substrate overlies a carrying surface of a chuck table of the semiconductor apparatus, an edge portion of the semiconductor substrate overlies a top surface of a first flexible member of the semiconductor apparatus, the first flexible member is disposed within a recess of the chuck table and extends along a perimeter of the carrying surface, and a gap forms among the semiconductor substrate, the carrying surface of the chuck table, and the top surface of the first flexible member; and introducing a vacuum in vacuum holes in the chuck table to form a vacuum seal among the semiconductor substrate, the chuck table, and the first flexible member.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Publication number: 20240332132
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Publication number: 20240304474
    Abstract: A pickup apparatus for separating a semiconductor package from an adhesive film includes a platform, a roller, a moving mechanism, and a collector element. The platform has a surface disposed with the adhesive film, where the adhesive film is disposed between the platform and the semiconductor package. The roller is disposed inside the platform and under the adhesive film, where the roller includes a body and a plurality of protrusions distributed over the body. The moving mechanism is connected to the roller to control a movement of the roller. The collector element is disposed over the platform and the adhesive film, where the collector element is configured to remove the semiconductor package from the adhesive film.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Ching-Hua Hsieh, Chih-Wei Lin, Hsiao-Chung Liang, Ying-Jui Huang
  • Patent number: 12040255
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Publication number: 20240234210
    Abstract: An integrated circuit package including integrated circuit dies and a method of forming are provided. The integrated circuit package may include a first integrated circuit die and a second integrated circuit die bonded to the first integrated circuit die. The first integrated circuit die may include a first substrate, a first interconnect structure, and a first bonding layer. The first interconnect structure may be between the first bonding layer and the first substrate. The second integrated circuit die may include a second substrate, a second interconnect structure, and a second bonding layer. The second interconnect structure may be between the second bonding layer and the second substrate. A first surface of the first bonding layer may be in direct contact with a first surface of the second bonding layer. A sidewall the first bonding layer and the first surface of the second bonding layer may form a first acute angle.
    Type: Application
    Filed: January 9, 2023
    Publication date: July 11, 2024
    Inventors: Jen-Chun Liao, Yen-Hung Chen, Ching-Hua Hsieh, Sung-Yueh Wu, Chih-Wei Lin, Kung-Chen Yeh
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Publication number: 20230386974
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Publication number: 20230387039
    Abstract: A semiconductor package includes a first package component comprising: an integrated circuit die; an encapsulant surrounding the integrated circuit die; and a fan-out structure electrically connected to the integrated circuit die, wherein a first opening extends completely through the fan-out structure and at least partially through the encapsulant in a cross-sectional view, and wherein the encapsulant at least completely surrounds the first opening in a top-down view. The semiconductor package further includes a package substrate bonded to the first package component.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 30, 2023
    Inventors: Sung-Yueh Wu, Jen-Chun Liao, Mao-Yen Chang, Yu-Chia Lai, Chien Ling Hwang, Ching-Hua Hsieh
  • Publication number: 20230378040
    Abstract: A package structure includes a carrier substrate, a die, and an encapsulant. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The conductive posts face away from the carrier substrate. The encapsulant laterally encapsulates the die.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
  • Patent number: 11764127
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Patent number: 11756872
    Abstract: A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
  • Publication number: 20230268316
    Abstract: A package structure includes a semiconductor device including a conductive feature, a joint layer, a pillar structure, an encapsulant and a RDL structure. The joint layer is disposed on the conductive feature. The pillar structure is disposed on and coupled to the semiconductor device through the joint layer. The encapsulant laterally encapsulates the semiconductor device and the pillar structure. The RDL structure is electrically connected to the semiconductor device.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh
  • Publication number: 20220319903
    Abstract: An apparatus and a method for handling a semiconductor substrate are provided. The apparatus includes a chuck table and a first flexible member. The chuck table includes a carrying surface, a first recess provided within the carrying surface, and a vacuum channel disposed below the carrying surface, and the chuck table is configured to hold the semiconductor substrate. The first flexible member is disposed within the first recess and includes a top surface protruded from the first recess, and the first flexible member is compressed as the semiconductor substrate presses against the first flexible member.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 6, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Publication number: 20220293505
    Abstract: A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
  • Publication number: 20220278023
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Patent number: 10985135
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Jen-Chun Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20200118969
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Jen-Chun Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu