Patents by Inventor JEN-CHUN YANG

JEN-CHUN YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Patent number: 11942130
    Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Jhong Chen, Yi-Ting Wu, Jen-Yu Wang, Cheng-Tung Huang, Po-Chun Yang, Yung-Ching Hsieh
  • Publication number: 20160153119
    Abstract: A Group-III nitrides epitaxial structure includes a Si substrate, and a Group-III nitrides layer disposed over the Si substrate, wherein an interface structure of “coexistence of Al atoms and SixNy” between the Si substrate and the Group-III nitrides. Al atoms are configured to be absorbed to the Si substrate and connect the Group-III nitrides; and SixNy are configured to release mismatch stress caused by heteroepitaxy. A fabricating method comprises: (1) providing a Si substrate; (2) forming an interface structure over a surface of the Si substrate , wherein the interface structure is arranged with both Al atoms and SixNy, which are then cladded by an AlN epitaxial layer; and (3) growing Group-III nitrides over the interface structure wherein the Al atoms are configured to be absorbed to the Si substrate and connect the Group-III nitrides and the SixNy is configured to release mismatch stress generated by heteroepitaxy.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 2, 2016
    Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: YANHAO DU, MENG-HSIN YEH, CHEN-KE HSU, CHIH-WEI CHAO, WENYU LIN, YI-SHIN YE, JEN-CHUN YANG, JIANMING LIU