Abstract: A pulse width modulation (PWM) driver and an operation method thereof are provided. The PWM driver includes a PWM generating circuit and multiple driving channels. The PWM generating circuit generates multiple PWM signals. The driving channels drive multiple light emitting elements of a light emitting element array. Each of the driving channels includes a PWM selection circuit. The PWM selection circuits are coupled to the PWM generating circuit to receive the PWM signals. Each of the PWM selection circuits selects a PWM signal from the PWM signals according to corresponding sub-pixel data. The selected PWM signal is output to at least one corresponding light emitting element among the light emitting elements.

Abstract: A pulse width modulation (PWM) driver and an operation method thereof are provided. The PWM driver includes a PWM generating circuit and multiple driving channels. The PWM generating circuit generates multiple PWM signals. The driving channels drive multiple light emitting elements of a light emitting element array. Each of the driving channels includes a PWM selection circuit. The PWM selection circuits are coupled to the PWM generating circuit to receive the PWM signals. Each of the PWM selection circuits selects a PWM signal from the PWM signals according to corresponding sub-pixel data. The selected PWM signal is output to at least one corresponding light emitting element among the light emitting elements.

Abstract: A display driving device and a method for driving a display are provided. The display driving device includes a host and a driving chip. The host transmits an image data and a synchronization signal. The driving chip receives the image data and the synchronization signal and drives a display panel to display frames. The driving chip includes a storage unit, a driving module, and a control circuit. The storage unit stores the image data. The driving module drives the display panel to display the frames according to the image data from the host and a timing generator frequency of the driving module. The control circuit detects a target frequency of the synchronization signal and the timing generator frequency of the driving module, compares the target frequency and the timing generator frequency, outputs an adjustment value according to the comparison result, and adjusts the timing generator frequency of driving module.

Abstract: A display driving device and a method for driving a display are provided. The display driving device includes a host and a driving chip. The host transmits an image data and a synchronization signal. The driving chip receives the image data and the synchronization signal and drives a display panel to display frames. The driving chip includes a storage unit, a driving module, and a control circuit. The storage unit stores the image data. The driving module drives the display panel to display the frames according to the image data from the host and a timing generator frequency of the driving module. The control circuit detects a target frequency of the synchronization signal and the timing generator frequency of the driving module, compares the target frequency and the timing generator frequency, outputs an adjustment value according to the comparison result, and adjusts the timing generator frequency of driving module.

Abstract: A frequency-converting circuit and a down converter with the frequency-converting circuit are disclosed. The above-mentioned frequency-converting circuit is used for converting an RF signal into a first baseband signal according to a poly-phase LO signal. The frequency-converting circuit includes a coupler, a first transduction unit and a first switching unit. The coupler is for receiving and splitting the RF signal and delivering a first RF signal via the first output terminal thereof. The first transduction unit is for amplifying the first RF signal. The first switching unit is for performing switching operations on the output signal of the first transduction unit and producing the first baseband signal.

Abstract: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Abstract: Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed.

Abstract: Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed.

Abstract: A sub-harmonic mixer and a down converter with the sub-harmonic mixer are provided. The sub-harmonic mixer includes a differential amplifying unit, a current buffer unit, and a switching unit. The differential amplifying unit is used to amplify a radio frequency (RF) signal and employs a first resonance circuit to force a leakage signal to flow to a first voltage. The current buffer unit is used to amplify the gain of an output signal of the differential amplifying unit and employs a second resonance circuit to force the leakage signal to flow to a second voltage. Finally, the switching unit switches an output signal of the current buffer unit into a base band signal.

Abstract: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Abstract: An inductor layout and manufacturing method thereof are provided. The inductor layout includes a substrate and a conductive path. The substrate includes at least an active region, wherein the active region includes at least a circuit. The conductive path is disposed over the substrate and arranged near the edge of the active region along the direction of the edge of the active region. Wherein, two ends of the conductive path are the two ends of the inductor.

Abstract: A sub-harmonic mixer and a down converter with the sub-harmonic mixer are provided. The sub-harmonic mixer includes a differential amplifying unit, a current buffer unit, and a switching unit. The differential amplifying unit is used to amplify a radio frequency (RF) signal and employs a first resonance circuit to force a leakage signal to flow to a first voltage. The current buffer unit is used to amplify the gain of an output signal of the differential amplifying unit and employs a second resonance circuit to force the leakage signal to flow to a second voltage. Finally, the switching unit switches an output signal of the current buffer unit into a base band signal.

Abstract: A frequency-converting circuit and a down converter with the frequency-converting circuit are disclosed. The above-mentioned frequency-converting circuit is used for converting an RF signal into a first baseband signal according to a poly-phase LO signal. The frequency-converting circuit includes a coupler, a first transduction unit and a first switching unit. The coupler is for receiving and splitting the RF signal and delivering a first RF signal via the first output terminal thereof. The first transduction unit is for amplifying the first RF signal. The first switching unit is for performing switching operations on the output signal of the first transduction unit and producing the first baseband signal.

Abstract: A transmit-receive switch for ultrawideband and a method for isolating transmitting and receiving signal thereof are provided. The transmit-receive switch includes a first switch, a second switch, and an inductor. The first switch has a first end coupled to a signal transmitting end, a second end coupled to a signal transmit-receive end, and a control end receiving a first control signal to decide whether or not to turn on the first switch according to the first controlling signal. The second switch has a first end coupled to a signal receiving end, a second end coupled to the signal transmit-receive end, and a control end receiving a second control signal to decide whether or not to turn on the second switch according to the second controlling signal. The inductor has an end coupled to the signal transmit-receive end, and another end coupled to a first potential.