Patents by Inventor Jen-Chung Chen
Jen-Chung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240113646Abstract: A method of obtaining a parameter of a synchronous motor is disclosed and includes: setting an operating current of the motor; providing a positive fixed voltage to the motor and monitoring a feedback current from the motor; recording a triggering time for the feedback current to reach the operating current; providing a negative fixed voltage to the motor for the triggering time; obtaining a square-wave voltage with a fixed frequency based on the positive fixed voltage and the negative fixed voltage being provided; providing the square-wave voltage with the fixed frequency to one axis of the motor; transforming three-phase current from the motor into an axial current; computing an inductance value of this axis based on the fixed frequency, the square-wave voltage and the axial current; and, creating an inductance-current parameter table based on a plurality of the inductance values and the axial currents correspondingly.Type: ApplicationFiled: January 18, 2023Publication date: April 4, 2024Inventors: Yen-Yang CHEN, Jen-Chih TSENG, Lei-Chung HSING
-
Publication number: 20230067848Abstract: A three-terminal power line fault location and correction system and method, and a computer readable storage medium. An electronic device is electrically connected with a plurality of terminal devices. When a fault occurs at a certain position of the power line, each terminal device detects the fault to generate a fault distance corresponding to the fault. The electronic device corrects the fault distance as follows: the corrected fault distance of one of the terminal devices=(an actual distance between the terminal device and a divergence point+a function of actual distances between the other two terminal devices and the divergence point)*the fault distance corresponding to the terminal device/(the fault distance corresponding to the terminal device+the fault distance corresponding to a function of the actual distances between the other two terminal devices and the divergence point).Type: ApplicationFiled: July 14, 2022Publication date: March 2, 2023Inventors: JUI-NIEN CHOU, SHUN-PIN CHEN, JEN-CHUNG CHEN
-
Publication number: 20190209608Abstract: A drinking water composition for improving the metabolism comprises magnesium, sodium, potassium, calcium and at least one of trace elements selected from the group consisting of chromium, boron, silicon, zinc, selenium, molybdenum, iodine and combinations thereof, in specific proportions. It is experimentally found that the drinking water composition can not only activate the expression of blood glucose regulation genes, but also has a positive impact on the fat storage capacity of cells, and can achieve the effect of improving the metabolism.Type: ApplicationFiled: January 5, 2018Publication date: July 11, 2019Inventors: JEN-CHUNG CHEN, CHIH-HUNG LIN
-
Publication number: 20170194162Abstract: A semiconductor manufacturing equipment includes a processing chamber, at least one reflector and at least one electromagnetic wave emitting device. The reflector is present in the processing chamber. The electromagnetic wave emitting device is present between the reflector and a wafer in the processing chamber. The electromagnetic wave emitting device is configured to emit a spectrum of electromagnetic wave to the wafer. The reflector has a relative reflectance to Al2O3 with respect to the spectrum of electromagnetic wave, and the relative reflectance of the reflector is in a range from about 70% to about 120%.Type: ApplicationFiled: January 5, 2016Publication date: July 6, 2017Inventors: Hsin-Chih LIU, Chia-Hung HUANG, Jen-Chung CHEN, Tung-Ching TSENG
-
Patent number: 9605345Abstract: A vertical furnace includes a heat treatment tube, at least one reactive gas inlet, first adiabatic plates and second adiabatic plates. The at least one reactive gas inlet is disposed at or near a bottom end of the heat treatment tube. The first adiabatic plates are stacked in the heat treatment tube, each of the first adiabatic plates having a flow channel structure for allowing a gas to pass through, in which all the corners in the flow channel structure are rounded. The second adiabatic plates are stacked below the first adiabatic plates in the heat treatment tube.Type: GrantFiled: August 23, 2013Date of Patent: March 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Eddy Lay, Shih-Min Tseng, Sheng-Wei Wu, Jen-Chung Chen, Shih-Fang Chen
-
Publication number: 20150053136Abstract: A vertical furnace includes a heat treatment tube, at least one reactive gas inlet, first adiabatic plates and second adiabatic plates. The at least one reactive gas inlet is disposed at or near a bottom end of the heat treatment tube. The first adiabatic plates are stacked in the heat treatment tube, each of the first adiabatic plates having a flow channel structure for allowing a gas to pass through, in which all the corners in the flow channel structure are rounded. The second adiabatic plates are stacked below the first adiabatic plates in the heat treatment tube.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Eddy Lay, Shih-Min Tseng, Sheng-Wei Wu, Jen-Chung Chen, Shih-Fang Chen
-
Patent number: 8157621Abstract: A wafer back side grinding process. A workpiece comprising a first assembly having a first semiconductor wafer and a second assembly having a second semiconductor wafer is provided. A first back side of the first semiconductor wafer is grinded by using the second assembly as a carrier. Thereafter, a second back side of the second semiconductor wafer is grinded.Type: GrantFiled: October 12, 2009Date of Patent: April 17, 2012Assignee: Nanya Technology Corp.Inventor: Jen-Chung Chen
-
Patent number: 8143712Abstract: A die package structure, which comprises: a first die; a second die; a core material layer, provided between the first die and the second die; at least one via, penetrating through the first die, the second die and the core material layer; a metal material, stuffing into the via, such that the first die the second die, and the core material layer can be electrically contacted with each other; at least a signal contacting unit, contacting the metal material; and a dielectric layer, enclosing the first die, including at least one breach exposing the signal contacting unit.Type: GrantFiled: July 15, 2010Date of Patent: March 27, 2012Assignee: Nanya Technology Corp.Inventor: Jen-Chung Chen
-
Publication number: 20120013018Abstract: A die package structure, which comprises: a first die; a second die; a core material layer, provided between the first die and the second die; at least one via, penetrating through the first die, the second die and the core material layer; a metal material, stuffing into the via, such that the first die the second die, and the core material layer can be electrically contacted with each other; at least a signal contacting unit, contacting the metal material; and a dielectric layer, enclosing the first die, including at least one breach exposing the signal contacting unit.Type: ApplicationFiled: July 15, 2010Publication date: January 19, 2012Inventor: Jen-Chung Chen
-
Patent number: 7948073Abstract: A three-dimensional package includes a carrier, a first die mounted on a first surface of the carrier, and a second die stacked on the first die. The first die includes first bond pads and second bond pads juxtaposed in separate two rows within a central region of the first die. The package further includes first bond fingers disposed on the first surface along a first side of the carrier, and second bond fingers along a second side opposite to the first side. A first bond wire is bonded to one of the first bond pads and extends to one the first bond fingers. The first bond wire overlies the row of the second bond pads. A second bond wire is bonded to one of the second bond pads and extends to one the second bond fingers. The second bond wire overlies the row of the first bond pads.Type: GrantFiled: March 19, 2009Date of Patent: May 24, 2011Assignee: Nanya Technology Corp.Inventor: Jen-Chung Chen
-
Publication number: 20110117232Abstract: A semiconductor chip package is provided. A semiconductor chip package includes a base comprising a top surface and a bottom surface, the top surface comprising a die attach region and a through-hole forming region surrounding the die attach region, a die attached on the die attach region, a molding material encapsulating the die and a plurality of through holes filled up with the molding material formed in the through-hole forming region.Type: ApplicationFiled: November 18, 2009Publication date: May 19, 2011Inventor: Jen-Chung Chen
-
Publication number: 20110115067Abstract: A semiconductor chip package includes a base comprising a die attach region and a mold-lock forming region surrounding the die attach region; a die mounted onto the base within the die attach region; a plurality of line-shaped trenches in the mold-lock forming region; a mold body encapsulating the die; and a mold lock inlaid in each of the line-shaped trenches to securely interlock the mold body to the base.Type: ApplicationFiled: February 23, 2010Publication date: May 19, 2011Inventor: Jen-Chung Chen
-
Publication number: 20110084374Abstract: A semiconductor package includes a carrier substrate having thereon at least one bond finger; a semiconductor die mounted on a top surface of the carrier substrate; at least one active bond pad disposed on the semiconductor die; at least one dummy bond pad disposed on the semiconductor die; a first bonding wire extending between the at least one active bond pad and the at least one dummy bond pad; a second bonding wire extending between the at least one dummy bond pad and the at least one bond finger; and a molding compound encapsulating at least the semiconductor die.Type: ApplicationFiled: October 8, 2009Publication date: April 14, 2011Inventor: Jen-Chung Chen
-
Publication number: 20110086580Abstract: A wafer back side grinding process. A workpiece comprising a first assembly having a first semiconductor wafer and a second assembly having a second semiconductor wafer is provided. A first back side of the first semiconductor wafer is grinded by using the second assembly as a carrier. Thereafter, a second back side of the second semiconductor wafer is grinded.Type: ApplicationFiled: October 12, 2009Publication date: April 14, 2011Inventor: Jen-Chung Chen
-
Patent number: 7923852Abstract: A semiconductor package structure includes a carrier, a chip or multi-chips mounted on a top surface of the carrier, a molding compound encapsulating the top surface and the chips, a plurality of solder balls distributed on a bottom surface of the carrier, and a protection bar formed of thermosetting plastic material formed on the bottom surface.Type: GrantFiled: February 3, 2009Date of Patent: April 12, 2011Assignee: Nanya Technology Corp.Inventor: Jen-Chung Chen
-
Publication number: 20100171212Abstract: A semiconductor package structure includes a carrier, a chip or multi-chips mounted on a top surface of the carrier, a molding compound encapsulating the top surface and the chips, a plurality of solder balls distributed on a bottom surface of the carrier, and a protection bar formed of thermosetting plastic material formed on the bottom surface.Type: ApplicationFiled: February 3, 2009Publication date: July 8, 2010Inventor: Jen-Chung Chen
-
Publication number: 20100171204Abstract: A three-dimensional package includes a carrier, a first die mounted on a first surface of the carrier, and a second die stacked on the first die. The first die includes first bond pads and second bond pads juxtaposed in separate two rows within a central region of the first die. The package further includes first bond fingers disposed on the first surface along a first side of the carrier, and second bond fingers along a second side opposite to the first side. A first bond wire is bonded to one of the first bond pads and extends to one the first bond fingers. The first bond wire overlies the row of the second bond pads. A second bond wire is bonded to one of the second bond pads and extends to one the second bond fingers. The second bond wire overlies the row of the first bond pads.Type: ApplicationFiled: March 19, 2009Publication date: July 8, 2010Inventor: Jen-Chung Chen
-
Patent number: 5795996Abstract: A method for monitoring water quality including deriving calcium hardness and M alkalinity from the linear functional relation between calcium hardness and specific conductivity, and that between log value of M alkalinity and pH value, simplifying the temperature curve into a formula, and calculating directly the saturation index. A multipurpose and inexpensive automatic water quality monitoring apparatus that can be adapted for use in cooling towers, swimming pools, and boilers may be made from a combination of an conductivity meter, pH meter, and oxidation reduction potential meter commonly used in testing, and a simple algorithm of a central processing unit.Type: GrantFiled: June 30, 1997Date of Patent: August 18, 1998Assignee: Industrial Technology Research InstituteInventors: Chen-Chang Chang, Shu-Fei Chan, Dong-Yuan Lin, Jen-Chung Chen, Guo Chen Chen, Don H. C. Chen