Abstract: The present invention discloses a package substrate comprising an insulative carrier having a through-hole penetrating the top and bottom surfaces thereof; at least one first and second conductive layers comprising circuits respectively formed on the top and bottom surfaces and covering an opening of the through-hole; a conductive element set in the through-hole for electrically connecting the first and second conductive layers; a first metal layer formed on the first and/or the second conductive layer; and at least one chip receiving bay formed by removing a portion of the carrier from the upper to the lower surfaces until the second conductive layer is exposed for accommodating at least one chip therein on the exposed second conductive layer. The package structure has a reduced overall thickness and an enhanced heat-dissipation effect for the chip and prevents from humidity penetration. A manufacturing method for the package structure is also disclosed.

Abstract: The present invention discloses a chip package carrier and a fabrication method, which have the advantages of high reliability, thickness reduction and the scale reduction. The carrier and the method uses blind holes., which penetrates the substrate but external traces and external bonding pads, which cover the external traces. A chip can be installed and encapsulated directly on a first surface.

Abstract: The present invention discloses a manufacture method for a thin double-sided package substrate, which includes steps: providing a carrier; respectively forming a first conductive layer and a second conductive layer on the upper and lower surfaces of the carrier; forming a through-hole penetrating the first conductive layer and the carrier but not penetrating the second conductive layer; setting a conductive element in the through-hole to electrically connect the first conductive layer with the second conductive layer; forming desired circuits on the first conductive layer and/or the second conductive layer; forming a first metal layer on the first conductive layer and/or the second conductive layer; and removing the carrier located in a predetermined region to form a chip receiving bay.

Abstract: A fabrication method of a semiconductor package is applied to fabricate the package with the lead frame. The fabrication method includes: performing a surface treatment on a carrier; electroplating a plurality of metal-stacked layers on the surface of the carrier, wherein the top of the metal-stacked layer is a bonding surface and the bottom of the metal-stacked layer is a welding surface; performing a chip bonding step; forming a molding compound on the carrier; removing the carrier and performing a dicing step to form a plurality of semiconductor packages. The fabrication method of a semiconductor package also includes that forming a plurality of cavities on the carrier surface, electroplating the metal-stacked layer on the cavities, and then performing the chip bonding step, forming the molding compound on the carrier; remove the carrier and performing the dicing step. Using the foregoing steps can prevent the overflow situation without using any tape.

Abstract: A fabrication method of semiconductor and a structure thereof are disclosed herein. The present invention includes: providing a substrate; disposing a mask on the substrate, wherein the mask has a plurality of patterned openings to expose portions of the substrate; forming a metal layer on the exposed portions of the substrate; forming a surface treatment layer on the metal layer; removing the mask; performing a chip package step; and removing the substrate and the metal layer to form a height difference of semiconductor package with pads. The characteristic of the height difference not only can increase the thickness of the solder materials but also can easily check the soldering status.