Abstract: An interconnect structure comprises a first level metal wiring line patterned on a semiconductor substrate, an inter-metal dielectric (IMD) layer formed on the metal wiring line, a contact plug passing through the IMD layer and electrically connected to the top of the first level metal wiring line, and a second level metal wiring line patterned on the IMD layer and electrically connected to the top of the contact plug. A cap layer is sandwiched between the top of the IMD layer and the bottom of the second level metal wiring line.

Abstract: A metal capacitor in damascene structures is provided. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator, and acting as an etch stop layer. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A capacitor is located on the third insulator and the first Cu plug, the capacitor having an upper electrode, a capacitor dielectric and a bottom electrode with the same pattern each other, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the conducting wire.

Abstract: A metal capacitor in damascene structures is provided. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator, and acting as an etch stop layer. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A capacitor is located on the third insulator and the first Cu plug, the capacitor having an upper electrode, a capacitor dielectric and a bottom electrode with the same pattern each other, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the conducting wire.

Abstract: A method for forming a metal capacitor in a damascene process is provided. Before the metal capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. The stacked layers are then subjected to a masking process and an etching process to form the thin-film capacitor and the metal wire with the remaining insulator and the remaining second metal layer thereon. The remaining second metal layer located on the metal wire is removed by another masking process and another etching process. After forming the capacitor and the metal wire, the upper interconnections are fabricated with Cu metal by damascene processes.