Patents by Inventor Jen-Hao Pan

Jen-Hao Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250132232
    Abstract: An electronic device is provided. The electronic device includes a first circuit structure, a second circuit structure, a conductive layer, and a supporting structure. The conductive layer is disposed between the first circuit structure and the second circuit structure.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 24, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Jen-Hao PAN
  • Publication number: 20240413062
    Abstract: A package structure is provided. The package structure includes a wiring structure, a first element, and a plurality of first wires. The wiring structure has a first recess recessed from a first surface of the wiring structure. The first element is disposed over the first surface of the wiring structure. The first wires are disposed in the first recess and extending in a direction from the wiring structure to the first element. The first wires are configured to reduce an inclination of the first element with respect to the first surface of the wiring structure.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Jen-Hao PAN
  • Patent number: 10680145
    Abstract: The present disclosure provides an LED package structure and a method for manufacturing the LED package structure. The LED package structure includes: a chip scale package (CSP) light emitting element and a shading layer, where the CSP light emitting element includes a light emitting chip, and the light emitting chip includes an electrode group located on a bottom surface of the light emitting chip, the shading layer is disposed on a bottom surface and/or a side surface of the CSP light emitting element. An LED package structure according to the present disclosure solves a problem that the blue light leaking from the bottom surface of the LED chip interferes with the emission color of the CSP emitting device, and reduces the luminous efficiency of the emitting device.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 9, 2020
    Assignee: EVERLIGHT ELECTRONICS CO., LTD.
    Inventors: Ke-Hao Pan, Sheng-Wei Chou, Yi-Sheng Lan, Chia-Fong Chou, Chung-Chuan Hsieh, Jen-Hao Pan, Hao-Yu Yang, Chieh-Yu Kang, Tzu-Lun Tseng
  • Publication number: 20190044036
    Abstract: The present disclosure provides an LED package structure and a method for manufacturing the LED package structure. The LED package structure includes: a chip scale package (CSP) light emitting element and a shading layer, where the CSP light emitting element includes a light emitting chip, and the light emitting chip includes an electrode group located on a bottom surface of the light emitting chip, the shading layer is disposed on a bottom surface and/or a side surface of the CSP light emitting element. An LED package structure according to the present disclosure solves a problem that the blue light leaking from the bottom surface of the LED chip interferes with the emission color of the CSP emitting device, and reduces the luminous efficiency of the emitting device.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 7, 2019
    Inventors: KE-HAO PAN, SHENG-WEI CHOU, YI-SHENG LAN, CHIA-FONG CHOU, CHUNG-CHUAN HSIEH, JEN-HAO PAN, HAO-YU YANG, CHIEH-YU KANG, TZU-LUN TSENG
  • Patent number: 7742266
    Abstract: An ESD/EOS protection circuit includes a first protection circuit and a second protection circuit. The first protection circuit is coupled between an I/O pad and a power pad and includes a first P-type transistor. The P-type transistor includes a control node, a floating gate, a first connection node, and a second connection node, wherein the first connection node of the first P-type transistor is coupled to the power pad and the second connection node of the first P-type transistor is coupled to the I/O pad. The second protection circuit is coupled between the I/O pad and a ground pad.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: June 22, 2010
    Assignee: ALI Corporation
    Inventors: Yu-Chen Chen, Jen-Hao Pan, Chih-Kuo Sun
  • Publication number: 20090073619
    Abstract: An ESD/EOS protection circuit includes a first protection circuit and a second protection circuit. The first protection circuit is coupled between an I/O pad and a power pad and includes a first P-type transistor. The P-type transistor includes a control node, a floating gate, a first connection node, and a second connection node, wherein the first connection node of the first P-type transistor is coupled to the power pad and the second connection node of the first P-type transistor is coupled to the I/O pad. The second protection circuit is coupled between the I/O pad and a ground pad.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 19, 2009
    Inventors: Yu-Chen Chen, Jen-Hao Pan, Chih-Kuo Sun