Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

Abstract: A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.

Abstract: An infrared photodetector structure with voltage-tunable and -switchable photoresponses constructed of superlattices and blocking barriers. The photoresponses of the double-superlattice structure are also insensitive to the operating temperature changes. By using GaAs/AlxGa1-xAs system, the feasibility of this idea is verified. In the embodiment, the photoresponses can be switched between 6˜8.5 and 7.5˜12 m by the bias polarity and are also tunable by the bias magnitude in each detection wavelength range. In addition, the photoresponses are insensitive to operating temperatures ranging from 20 to 80 K. For the SLIP with few periods, the responsivity may be higher than the one with many periods and the operational temperature is higher. These results show the invention can be useful in the design of multicolor imaging systems.

Abstract: An infrared photodetector structure with voltage-tunable and -switchable photoresponses constructed of superlattices and blocking barriers. The photoresponses of the double-superlattice structure are also insensitive to the operating temperature changes. By using GaAs/AlxGa1-xAs system, the feasibility of this idea is verified. In the embodiment, the photoresponses can be switched between 6˜8.5 and 7.5˜12 m by the bias polarity and are also tunable by the bias magnitude in each detection wavelength range. In addition, the photoresponses are insensitive to operating temperatures ranging from 20 to 80 K. For the SLIP with few periods, the responsivity may be higher than the one with many periods and the operational temperature is higher. These results show the invention can be useful in the design of multicolor imaging systems.