Patents by Inventor Jen-Hung Chiang

Jen-Hung Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240223099
    Abstract: A power detecting circuit board and, a power detecting system, and an immersed liquid cooling tank are provided, the power detecting system includes a plurality of power detecting circuit boards and a BMC, each power detecting circuit board is connected to at least one PSU, one of the power detecting circuit boards serves as a leader detecting circuit board, the rest of the power detecting circuit boards serve as follower detecting circuit boards; the leader detecting circuit board obtains running data of the corresponding PSU; each follower detecting circuit board obtains running data of the corresponding PSU; the leader detecting circuit board obtains the running data of the PSU corresponding to the follower detecting circuit boards, and summarize the running data of the PSU corresponding to the leader detecting circuit board and the running data of the PSU corresponding to the follower detecting circuit boards.
    Type: Application
    Filed: June 1, 2023
    Publication date: July 4, 2024
    Inventors: DUO QIU, LI-QUAN HE, JEN-HUNG CHIANG
  • Patent number: 8181342
    Abstract: Disclosed are a coreless packaging substrate and a manufacturing method thereof. The substrate includes a built-up structure and a first wiring layer. The built-up structure has a first outside and an opposite second outside, and includes one or more second dielectric layers and second wiring layers, and a plurality of conductive vias. The second dielectric layers have first and second surfaces respectively facing the first and second outsides. The second wiring layers are disposed on the second surface. The conductive vias are disposed in the second dielectric layer. The outermost second wiring layer at the second outside has a plurality of second conductive pads. The first wiring layer is embedded into and exposed from the first surface of the outermost second dielectric layer at the first outside, and has a plurality of first conductive pads. The conductive vias electrically connect the first wiring layer and the second wiring layer.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: May 22, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Jen-Hung Chiang, Chao-Meng Cheng
  • Publication number: 20100288549
    Abstract: Disclosed are a coreless packaging substrate and a manufacturing method thereof. The substrate includes a built-up structure and a first wiring layer. The built-up structure has a first outside and an opposite second outside, and includes one or more second dielectric layers and second wiring layers, and a plurality of conductive vias. The second dielectric layers have first and second surfaces respectively facing the first and second outsides. The second wiring layers are disposed on the second surface. The conductive vias are disposed in the second dielectric layer. The outermost second wiring layer at the second outside has a plurality of second conductive pads. The first wiring layer is embedded into and exposed from the first surface of the outermost second dielectric layer at the first outside, and has a plurality of first conductive pads. The conductive vias electrically connect the first wiring layer and the second wiring layer.
    Type: Application
    Filed: December 8, 2009
    Publication date: November 18, 2010
    Applicant: Unimicron Technology Corp.
    Inventors: Jen-Hung Chiang, Chao-Meng Cheng