Patents by Inventor Jen-I Pi

Jen-I Pi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ELECTRONIC WEARABLE DEVICE
    Publication number: 20240126327
    Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
  • Shared source line memory architecture for flash cell byte-alterable high endurance data memory
    Patent number: 10910058
    Abstract: A memory array includes (a) multiple memory cells arranged into a plurality of bytes, (b) a separate word line connected to each byte, and (b) multiple shared source lines, each connected to at least two bytes, such that each byte in the array is addressable by a separate word line and by the shared source line. Due to this memory array architecture, a program operation on a first byte applies a shared source line voltage on a non-selected second byte (with an inhibit voltage applied to bit lines connected to the second byte), which creates a disturb condition that corresponds with a diagonal (or row) program disturb condition in a conventional memory array. The use of the shared source lines may reduce the required number of source line drivers, which reduces the overhead area of the memory array, and at same time, allow backward compatibility of traditional byte-alterable EEPROM.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 2, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Jen-I Pi, Kent Hewitt
  • SHARED SOURCE LINE MEMORY ARCHITECTURE FOR FLASH CELL BYTE-ALTERABLE HIGH ENDURANCE DATA MEMORY
    Publication number: 20200058355
    Abstract: A memory array includes (a) multiple memory cells arranged into a plurality of bytes, (b) a separate word line connected to each byte, and (b) multiple shared source lines, each connected to at least two bytes, such that each byte in the array is addressable by a separate word line and by the shared source line. Due to this memory array architecture, a program operation on a first byte applies a shared source line voltage on a non-selected second byte (with an inhibit voltage applied to bit lines connected to the second byte), which creates a disturb condition that corresponds with a diagonal (or row) program disturb condition in a conventional memory array. The use of the shared source lines may reduce the required number of source line drivers, which reduces the overhead area of the memory array, and at same time, allow backward compatibility of traditional byte-alterable EEPROM.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 20, 2020
    Applicant: Microchip Technology Incorporated
    Inventors: Jen-I Pi, Kent Hewitt