Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.