Abstract: An encryption and signature device for AI model protection is provided. The encryption and signature device for AI model protection includes a key derivation unit, a model encryption unit, a model password encryption unit, an image generation unit and a signature unit. The key derivation unit is configured to derive a model key according to a model password and a derivation function. The model encryption unit is configured to encrypt an AI model according to the model key to generate an encrypted AI model. The model password encryption unit is configured to encrypt the model password to generate an encrypted model password. The image generation unit is configured to generate an image file according to the encrypted model password and the encrypted AI model. The signature unit is configured to sign the image file according to a private key to obtain a signed image file.

Abstract: This invention provides methods of beam-indexed spatial modulation (BISM) for multiple-input and multiple-output (MIMO) technology. It does not only enhance the efficiency of MIMO using, but also address the compatibility problems in Spatial Modulation (SM-MIMO) and Orthogonal Frequency Division Multiplexing Index Modulation (OFDM-IM). Furthermore, the BISM improves the speed limitation problem and spectral efficiency issue in the current spatial modulation architectures.

Abstract: This invention provides methods of beam-indexed spatial modulation (BISM) for multiple-input and multiple-output (MIMO) technology. It does not only enhance the efficiency of MIMO using, but also address the compatibility problems in Spatial Modulation (SM-MIMO) and Orthogonal Frequency Division Multiplexing Index Modulation (OFDM-IM). Furthermore, the BISM improves the speed limitation problem and spectral efficiency issue in the current spatial modulation architectures.

Abstract: An antenna beam searching method uses a balance puzzle concept to perform group division of a plurality of antenna beams supported by a transmitter end, so as to perform evaluation on the antenna beam group(s) thus divided to determine an angle of departure of the transmitter end.

Abstract: A method for scheduling a pilot signal, a control node and a wireless device are proposed. The control node manages an i-th cell among N cells of a network cluster. The method includes: dividing a training time into at least (N) time slots; scheduling a wireless device of the i-th cell to transmit a first pilot signal at a j-th time slot and a (j+1)-th time slot, or scheduling the wireless device of the i-th cell to transmit a second pilot signal at the j-th time slot and the (j+1)-th time slot; scheduling the wireless device to alternately transmit the first pilot signal and the second pilot signal at residual time slots other than the j-th time slot and the (j+1)-th time slot, wherein the first pilot signal and the second pilot signal have opposite signs.

Abstract: A method for scheduling a pilot signal, a control node and a wireless device are proposed. The control node manages an i-th cell among N cells of a network cluster. The method includes: dividing a training time into at least (N) time slots; scheduling a wireless device of the i-th cell to transmit a first pilot signal at a j-th time slot and a (j+1)-th time slot, or scheduling the wireless device of the i-th cell to transmit a second pilot signal at the j-th time slot and the (j+1)-th time slot; scheduling the wireless device to alternately transmit the first pilot signal and the second pilot signal at residual time slots other than the j-th time slot and the (j+1)-th time slot, wherein the first pilot signal and the second pilot signal have opposite signs.

Abstract: A double quasi-cyclic low density parity check (DQC-LDPC) code and a corresponding processor are disclosed herein. The parity-check matrix of DQC-LDPC codes has regularity with its corresponding processor including an input end, an output end and a processing module. The parity-check matrix includes a double quasi-cyclic matrix. The double quasi-cyclic matrix includes a plurality of sub-matrices. The sub-matrices are arranged in an array. Each sub-matrix includes a plurality of entries, and each sub-matrix is a circulant matrix having the entries circular shifted row-by-row. The double quasi-cyclic matrix is a circulant matrix having the sub-matrices circular shifted row-by-row. The processing module is configured to process an input signal and output an output signal correspond to the parity-check matrix of a low density parity check code (LDPC).

Abstract: A double quasi-cyclic low density parity check (DQC-LDPC) code and a corresponding processor are disclosed herein. The parity-check matrix of DQC-LDPC codes has regularity with its corresponding processor including an input end, an output end and a processing module. The parity-check matrix includes a double quasi-cyclic matrix. The double quasi-cyclic matrix includes a plurality of sub-matrices. The sub-matrices are arranged in an array. Each sub-matrix includes a plurality of entries, and each sub-matrix is a circulant matrix having the entries circular shifted row-by-row. The double quasi-cyclic matrix is a circulant matrix having the sub-matrices circular shifted row-by-row. The processing module is configured to process an input signal and output an output signal correspond to the parity-check matrix of a low density parity check code (LDPC).

Abstract: A broadband high output current output stage includes at least one first differential pair for enhancing the bandwidth. A second differential pair is further disposed in the circuit. The second differential pair is coupled to one of the first differential pair, such that a large output voltage swing is distributed to all transistors to avoid breakdowns thereof. A feedback unit is connected between each bias unit and the first differential pair. The first compensation unit compensates the electric characteristic of the high-frequency zero of the feedback unit and the bias unit, thereby broadening the linear bandwidth of the frequency response. The second compensation units are disposed between the first differential pairs. Each second compensation unit compensates the high-frequency zero of the node where each two first differential pairs are cascaded, thereby further broadening the linear bandwidth of the frequency response.

Abstract: The invention discloses an active back-end termination circuit, which comprises a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor and the first transistor are connected in series for forming a first impendence unit. A first source of the first transistor is connected to a working voltage with VTT. The second resistor and the second transistor are connected in series for forming a second impendence unit. A second gate and a second drain of the second transistor are connected to the working voltage with VTT. Wherein, the first impendence unit and the second impendence unit are connected in parallel. The first transistor or the second transistor is switched on through a power source, and the first transistor and the second transistor change the impedance actively for matching a load according to the voltage source.

Abstract: The invention discloses an active back-end termination circuit, which comprises a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor and the first transistor are connected in series for forming a first impendence unit. A first source of the first transistor is connected to a working voltage with VTT. The second resistor and the second transistor are connected in series for forming a second impendence unit. A second gate and a second drain of the second transistor are connected to the working voltage with VTT. Wherein, the first impendence unit and the second impendence unit are connected in parallel. The first transistor or the second transistor is switched on through a power source, and the first transistor and the second transistor change the impedance actively for matching a load according to the voltage source.

Abstract: A broadband high output current output stage includes at least one first differential pair for enhancing the bandwidth. A second differential pair is further disposed in the circuit. The second differential pair is coupled to one of the first differential pair, such that a large output voltage swing is distributed to all transistors to avoid breakdowns thereof. A feedback unit is connected between each bias unit and the first differential pair. The first compensation unit compensates the electric characteristic of the high-frequency zero of the feedback unit and the bias unit, thereby broadening the linear bandwidth of the frequency response. The second compensation units are disposed between the first differential pairs. Each second compensation unit compensates the high-frequency zero of the node where each two first differential pairs are cascaded, thereby further broadening the linear bandwidth of the frequency response.

Abstract: A transmission circuit includes a first-stage circuit, a second-stage circuit, a negative active feedback circuit and a current buffer. The first-stage circuit includes at least an active MOS device for receiving an input voltage and issuing a first voltage signal. The active MOS device has an inductive feature during operation in a high frequency mode to compensate the first voltage signal. In response to the first voltage signal, the second-stage circuit outputs a first output voltage. The negative active feedback circuit may enhance the bandwidth of the first output voltage. The current buffer may enhance the gain value of the first output voltage. A second voltage signal is issued from the first-stage circuit and compensated by the first output voltage transmitted from the current buffer to enhance the bandwidth and the gain value thereof. In response to the compensated second voltage signal, the second-stage circuit outputs a second output voltage.