Abstract: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. The DDR PSRAM also includes a data transmitter and a data strobe generating unit. The data transmitter obtains data stored in the address of the memory and provides a double data rate data to the controller according to the obtained data, and the data strobe generating unit a data strobe signal to the controller and toggling the data strobe signal in response to the double data rate data.

Abstract: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. The DDR PSRAM also includes a data transmitter and a data strobe generating unit. The data transmitter obtains data stored in the address of the memory and provides a double data rate data to the controller according to the obtained data, and the data strobe generating unit a data strobe signal to the controller and toggling the data strobe signal in response to the double data rate data.

Abstract: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory.

Abstract: A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.

Abstract: A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.

Abstract: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory.

Abstract: The present invention discloses a speed adjustment system and method for performing the same, which is capable to provide different power saving behaviors adaptive for different applications (e.g. a mobile or a normal configuration) and/or different-corner-process chips. The speed adjustment system includes a reference speed generator for pre-storing multiple reference speed value, an operating speed generator for pre-storing multiple operating speed value, a comparing unit for determining whether a predefined logical operational relationship is satisfied with the operating speed value and reference speed value, a voltage controller based on said determination result to vary the operating voltage, and a speed detector for detecting the operating speed value.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: The present invention relates to a quasi-synchronous multi-stage event synchronization apparatus by a phase lock loop (PLL) control circuit and a quasi-synchronous multi-stage synchronizer to tolerate clock uncertainty and speed up the synchronizing process between the asynchronous digital circuits from producing-end to consuming-end in the computer system. The phase lock loop (PLL) control circuit generates a pair of well-controlled clocks, PDU_CLK, CSM_CLK, assigned to producing-end and consuming-end and a pair of clock phase indicating signals, PDU_SYNC_PULSE, CSM_SYNC_PULSE, associated with the pair of well-controlled clocks. The quasi-synchronous multi-stage synchronizer routes the series of sync events into a synchronization stage with minimal synchronization delay from producing-end to consuming-end.

Abstract: A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: The present invention discloses an apparatus and system for multi-stage event synchronization, whose main object is to eliminate the drawbacks of an expensive synchronization circuit used to balance the data transmissions between an origination agent and a destination agent operating at different frequencies or clock phases as in prior art. The apparatus of the present invention organizes the slower one with multi-stage chains, each of which comprises a simple synchronization circuit and an XOR gate, for receiving the number of events transmitted from the faster one. Therefore, the slower one will not miss the data from the faster one.

Abstract: In a memory controller system, a method for granting a system memory by a memory request arbitrator to a request among a plurality of pending memory access requests is provided. The plurality of the memory access requests includes Rfrsh_Hreq, Crt_Hreq, Group AB, Crt_Lreq and Rfrsh_Lreq and are respectively asserted by a host control circuitry and/or a graphical control circuitry which are implemented and integrated on a single monolithic semiconductor chip. The host control circuitry and the graphical control circuitry shares the system memory and the memory request arbitrator includes a refresh queue and the graphics control circuitry includes a CRT FIFO. The method prioritizes the plurality of the memory access requests in order of Rfrsh_Hreq>Crt_Hreq>Group AB>Crt_Lreq>Rfrsh_Lreq.