Patents by Inventor Jen-Po Lin

Jen-Po Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12363924
    Abstract: Embodiments of present disclosure provide a MIM capacitor including a straining layer on an electrode, and a high-k dielectric layer formed on the straining layer. The straining layer allows the high-k dielectric layer to be highly crystallized without requiring an extra annealing process. The high crystallization of the high-k dielectric layer results in increased the dielectric value (k-value), thus, improving capacitance density in the MIM capacitor. Some embodiments provide a MIM capacitor device including stacked MIM capacitors with symmetrically arranged high-k dielectric layers and straining layers.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: July 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Po Lin, Cherng-Yu Wang, Hsiao-Kuan Wei
  • Publication number: 20250203892
    Abstract: Embodiments of present disclosure provide a MIM capacitor device structure including a first conductive layer and a dielectric stack disposed on the first and second portions of the first conductive layer. The dielectric stack includes a first dielectric layer disposed on the first conductive layer, a high-k dielectric layer disposed on the first dielectric layer, and a second dielectric layer disposed on the high-k dielectric layer. The structure further includes a second conductive layer disposed on the dielectric stack, a first conductive feature extending through the first conductive layer and a first portion of the dielectric stack, and a second conductive feature extending through a second portion of the dielectric stack and the second conductive layer.
    Type: Application
    Filed: April 5, 2024
    Publication date: June 19, 2025
    Inventors: Jen-Po LIN, Hsiao-Kuan WEI, Man-Yun WU
  • Publication number: 20250167086
    Abstract: A method includes: forming a redistribution layer (RDL) comprising metal material over a substrate; forming an oxidation layer of the metal material on sidewalls of the RDL; and depositing a passivation layer over the RDL and the oxidation layer, wherein the oxidation layer is formed between the RDL and the passivation layer; wherein the oxidation layer strengthens bonding between the RDL and the passivation layer to resist hydrogen induced voids from forming. The method may allow for performing a hydrogen plasma annealing treatment without hydrogen-induced voiding in top or bottom corners of the RDL. A device includes: an RDL comprising metal material formed over a substrate; a passivation layer formed over the RDL; and an oxidation layer of the metal material formed on sidewalls of the RDL between the RDL and the passivation layer. The device may be formed without voids in top or bottom corners of the RDL.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 22, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Man-Yun Wu, Hsiao-Kuan Wei, Jen-Po Lin, Ssu-Yu Ho
  • Publication number: 20240387615
    Abstract: Embodiments of present disclosure provide a MIM capacitor including a straining layer on an electrode, and a high-k dielectric layer formed on the straining layer. The straining layer allows the high-k dielectric layer to be highly crystallized without requiring an extra annealing process. The high crystallization of the high-k dielectric layer results in increased the dielectric value (k-value), thus, improving capacitance density in the MIM capacitor. Some embodiments provide a MIM capacitor device including stacked MIM capacitors with symmetrically arranged high-k dielectric layers and straining layers.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Jen-Po LIN, Cherng-Yu WANG, Hsiao-Kuan WEI
  • Publication number: 20230403948
    Abstract: Embodiments of the present disclosure provide a magnetic tunnel junction (MTJ) structure for storing a data. In one embodiment, the MJT structure includes a first ferromagnetic layer, a second ferromagnetic layer disposed above the first ferromagnetic layer, a first dielectric layer disposed between and in contact with the first ferromagnetic layer and the second ferromagnetic layer, a plurality of metal particles disposed in contact with the second ferromagnetic layer, wherein the metal particles are distributed in a discrete and non-continuous manner, and a second dielectric layer disposed over the plurality of metal particles.
    Type: Application
    Filed: June 12, 2022
    Publication date: December 14, 2023
    Inventors: Hsuan-Yi PENG, Cherng-Yu WANG, Jen-Po LIN, Hsiao-Kuan WEI
  • Publication number: 20230395647
    Abstract: Embodiments of present disclosure provide a MIM capacitor including a straining layer on an electrode, and a high-k dielectric layer formed on the straining layer. The straining layer allows the high-k dielectric layer to be highly crystallized without requiring an extra annealing process. The high crystallization of the high-k dielectric layer results in increased the dielectric value (k-value), thus, improving capacitance density in the MIM capacitor. Some embodiments provide a MIM capacitor device including stacked MIM capacitors with symmetrically arranged high-k dielectric layers and straining layers.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Jen-Po LIN, Cherng-Yu WANG, Hsiao-Kuan WEI
  • Patent number: 7053019
    Abstract: A new dielectric material composition with high dielectric constant and low dielectric loss, which includes a quaternary metallic oxide having a pervoskite structure and represented by a general formula, Ba1-xM1xTi1-yM2yOm. It is suitable for Gbit memory devices, embedded capacitance devices in multilayered structures, and modulable capacitors for high frequency devices.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 30, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Li-Mei Chen, Chao-Jen Wang, Chien-Hsien Yu, Jen-Po Lin
  • Publication number: 20040089853
    Abstract: A new dielectric material composition with high dielectric constant and low dielectric loss, which includes a quaternary metallic oxide having a pervoskite structure and represented by a general formula, Ba1−xM1xTi1−yM2yOm. It is suitable for Gbit memory devices, embedded capacitance devices in multilayered structures, and modulable capacitors for high frequency devices.
    Type: Application
    Filed: June 27, 2003
    Publication date: May 13, 2004
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Mei Chen, Chao-Jen Wang, Chien-Hsien Yu, Jen-Po Lin