Abstract: A phase-change multi-level memory cell is described, including a semiconductor substrate, a gate structure, two S/D regions, and two phase-change storing units electrically connected to the two S/D regions respectively. One phase-change storing unit can be programmed to one of many phases having different electrical resistances, and combination variations of the phases of the two phase-change storing units generate different read currents corresponding to 2n n-bit data values (n?2). To program the cell, the phase of each phase-change storing unit is changed to one of the many phases mentioned above, so that the phase combination of the two phase-change storing units corresponds to a predetermined data value. In addition, when reading the memory cell, the read current is measured to obtain the data value stored.