Abstract: An analysis method and an electronic apparatus for breast image are provided. The method includes the following steps. One or more breast ultrasound images are obtained. The breast ultrasound images are used for forming a three-dimensional (3D) breast model. A volume of interest (VOI) in the breast ultrasound image is obtained by applying a detection model on the 3D breast model. The VOI is compared with a tissue segmentation result. The VOI is determined as a false positive according to a compared result between the VOI and the tissue segmentation result. The compared result includes that the VOI is located at a glandular tissue based on the tissue segmentation result. In response to the VOI being located in the glandular tissue of the tissue segmentation result, the VOI is compared with the lactiferous duct in the 3D breast model.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit provides a switch signal to a charge pump which provides a memory with a read voltage and a read current. The charge pump drive circuit includes a read drive circuit and a standby drive circuit. The read drive circuit is powered by a first power supply and provides the charge pump with a switch signal when the memory is in an active reading state. The standby drive circuit is powered by a second power supply and provides the charge pump with a switch signal when the memory is in a read standby state. The first power supply provides a voltage level ranging from 1.6 V to 3.8 V, and the second power supply provides a voltage level of 1.5 V.

Abstract: A local X-decoder for a memory system including a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and a voltage clamping transistor coupled to the decoding unit, and configured to reduce a voltage difference across a global word line signal and the word line signal by an amount of a threshold voltage of the voltage clamping transistor.

Abstract: A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

Abstract: A local X-decoder for a memory system including a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and a voltage clamping transistor coupled to the decoding unit, and configured to reduce a voltage difference across a global word line signal and the word line signal by an amount of a threshold voltage of the voltage clamping transistor.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit includes a first pulse generating circuit and a second pulse generating circuit. Each of the first pulse generating circuit and the second pulse generating circuit is configured to connect to a charge pump. The first pulse generating circuit is configured to provide the charge pump with a series of first pulse signals. The second pulse generating circuit is configured to generate a second pulse signal in response to and based on an address translation detection signal and provide the second pulse signal to the charge pump or to the first pulse generating circuit. The first pulse generating circuit generates an additional first pulse signals based on the second pulse signal.

Abstract: A circuit for regulating a leakage current in a charge pump is disclosed. The circuit includes a bias voltage generating circuit and a first transistor, wherein: the bias voltage generating circuit generates a bias voltage that is proportional to a supply voltage; a gate of the first transistor is coupled to the bias voltage; the first transistor has a drain that is coupled to an output of the charge pump and a source that is grounded; a voltage the drain of the first transistor is proportional to the supply voltage; and a current flowing through the source and drain of the first transistor is proportional to the supply voltage that powers the charge pump.

Abstract: A sensing circuit includes a plurality of cascode transistors including: a Flash memory cell; a sensing node; and an NMOS. The sensing circuit further includes a charge pump for generating an output voltage. A first output voltage is directly input to the plurality of cascode transistors during programming, and a second output voltage of the charge pump is coupled to a gate of the NMOS during a read to bias the NMOS. A sensing amplifier has an input coupled to the sensing node for receiving read data of the Flash memory cell when the NMOS is biased. A low-pass filter is coupled between the second output voltage of the charge pump and the gate of the NMOS.

Abstract: A voltage regulator includes a first feedback loop and a second feedback loop. The first feedback loop includes a charge pump outputting a first output voltage, a first transistor ladder and a control circuit. The first transistor ladder divides the first output voltage to generate a first feedback voltage. The control circuit receives the first feedback voltage and controls a level of the first output voltage according to the first feedback voltage and a reference voltage. The second feedback loop includes a power transistor, a second transistor ladder and an operational amplifier. The power transistor receives the first output voltage to output a second output voltage. The second transistor ladder divides the second output voltage to generate a second feedback voltage. The operational amplifier outputs a control signal to the power transistor by receiving the second feedback voltage and a reference voltage selected from one of a plurality of levels.

Abstract: A local X-decoder for a memory system includes a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and an unselected erase detecting unit coupled to the decoding unit, and configured to increase an absolute voltage coupled to the word line signal from a well of the memory cell according to an unselected erase mode signal generated by an erase mode decoder of the memory system; wherein the word line signal is floating to a same level as the well of the memory cell when the memory cell is unselected in an erase mode of the memory system.

Abstract: A two-sided memory array is disclosed. Each side includes four local x-decoders. Each local x-decoder includes: a first pair of cascode transistors coupled to a first signal; a second pair of cascode transistors coupled to the first signal, a second signal, and a word line; a third transistor coupled to the first signal; and a third pair of cascode transistors coupled to the second signal, a third signal, and the word line. All transistors in each local x-decoder are disposed vertically, and P-channels and N-channels on each side of the memory array are disposed in an order corresponding to P-channels of a first local x-decoder, P-channels of a second local x-decoder, P-channels of a third local x-decoder, P-channels of a fourth local x-decoder, N-channels of the fourth local x-decoder, N-channels of the third local x-decoder, N-channels of the second local x-decoder and N-channels of the first local x-decoder.

Abstract: A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit provides a switch signal to a charge pump which provides a memory with a read voltage and a read current. The charge pump drive circuit includes a read drive circuit and a standby drive circuit. The read drive circuit is powered by a first power supply and provides the charge pump with a switch signal when the memory is in an active reading state. The standby drive circuit is powered by a second power supply and provides the charge pump with a switch signal when the memory is in a read standby state. The first power supply provides a voltage level ranging from 1.6 V to 3.8 V, and the second power supply provides a voltage level of 1.5 V.

Abstract: A charge pump is disclosed, including: multiple charge-pump stages connected sequentially; multiple switches, coupled between output of a corresponding one of charge-pump stages and output of charge pump; multiple second switches, coupled, at one end, to output of a corresponding one of charge-pump stages and to input of immediately succeeding one of charge-pump stages at other end; and multiple third switch, coupled between output of corresponding one of charge-pump stages and input of charge pump. First, second and third switches are opened or closed to determine a number of charge-pump stages connected in series and a number of charge-pump stages connected in parallel. The greater the number of charge-pump stages connected in series in charge-pump cascade is, the higher output voltage of charge pump will be, and the greater the number of charge-pump stages connected in parallel in charge-pump cascade, the higher drive current produced by charge pump will be.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit includes a first pulse generating circuit and a second pulse generating circuit. Each of the first pulse generating circuit and the second pulse generating circuit is configured to connect to a charge pump. The first pulse generating circuit is configured to provide the charge pump with a series of first pulse signals. The second pulse generating circuit is configured to generate a second pulse signal in response to and based on an address translation detection signal and provide the second pulse signal to the charge pump or to the first pulse generating circuit. The first pulse generating circuit generates an additional first pulse signals based on the second pulse signal.

Abstract: A circuit for regulating a leakage current in a charge pump is disclosed. The circuit includes a bias voltage generating circuit and a first transistor, wherein: the bias voltage generating circuit generates a bias voltage that is proportional to a supply voltage; a gate of the first transistor is coupled to the bias voltage; the first transistor has a drain that is coupled to an output of the charge pump and a source that is grounded; a voltage the drain of the first transistor is proportional to the supply voltage; and a current flowing through the source and drain of the first transistor is proportional to the supply voltage that powers the charge pump.

Abstract: A charge pump system includes: a differential amplifier, for receiving a feedback voltage and a reference voltage and generating an output signal; an oscillating circuit for generating clock pulses; a charge pump for receiving the clock pulses and generating an output voltage; a current sink coupled to the output of the charge pump; a first pair of cascode transistors for generating a digital signal; and an inverter for inverting the digital signal to generate a first digital signal according to the output signal, wherein the first digital signal is input to the current sink. When the feedback voltage is higher than the reference voltage, the first digital signal will be generated and the current sink will be turned on, and when the feedback voltage is lower than the reference voltage, the first digital signal will not be generated and the current sink will be turned off.

Abstract: ESD clamp circuit is provided, including an RC circuit, a first transistor, a second transistor, an ESD conduction unit and an inverter. The first transistor has a gate and a drain respectively coupled to the RC circuit and a control terminal of the ESD conduction unit. The inverter has an input terminal coupled to the control terminal. The second transistor has a drain and a gate respectively coupled to the control terminal and an output terminal of the inverter. The gates of the first and second transistors are isolated; also the output terminal and the gate of the first transistor are isolated.

Abstract: A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.

Abstract: A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.