Abstract: The present invention provides a color-mixing light-emitting diode module. According to the present invention, a first light-emitting chip and two second light-emitting chips are disposed on a holder. The first light-emitting chip emits red light and the plurality of second light-emitting chips emit white light. The red light and the white light are mixed, giving mixed light with high color rendering and brightness. Objects illuminated by the mixed light will exhibit colors closest to their original colors as perceived by eyes. Furthermore, by arranging the first and second light-emitting chips in matrix, the color rendering of the light-emitting diode module can be adjusted and improved.

Abstract: The present invention provides a light-emitting module, which comprises a light-emitting device, a light-guiding member, and an external light-guiding member. The light-emitting device emits light. The light-guiding member is disposed on the light-emitting path of the light-emitting module; the external light-guiding member is disposed on the light-emitting path of the light-emitting member. The light-guiding member distributes the light over the light-incidence surface of the external light-guiding member uniformly. After the external light-guiding member, the light is modified to axially symmetric light. Besides, the light-emitting device is disposed in a reflection ring, and a diffuser is disposed on the light-emitting path of the light-emitting device. When a minority of the light-emitting device fail, although the overall energy of the light source is reduced, the influence on the light emission of the light-emitting module is not significant.

Abstract: The present invention provides an LED module capable of blue-light energy, which mainly comprises a blue LED chip and a packaging glue. The blue LED chip emits blue light. The packaging glue covers the light-emitting path of the blue LED chip. The packaging glue further includes a fluorescent powder. The amount of the fluorescent powder occupies 10% to 40% of the amount of the packaging glue. After the blue light excites the fluorescent powder, the white light is generated. The hue of the white light falls in hue coordinates (CIE 1931) and 8 nominal CCT ranges in the chromaticity diagram. The present invention controls the proportion of the fluorescent powder in the packaging glue, so that the blue light consumes most of its energy on exciting the fluorescent powders. Thereby, the proportion of the blue light in the white light is fewer.

Abstract: The present invention provides a color-mixing light-emitting diode module. According to the present invention, a first light-emitting chip and two second light-emitting chips are disposed on a holder. The first light-emitting chip emits red light and the plurality of second light-emitting chips emit white light. The red light and the white light are mixed, giving mixed light with high color rendering and brightness. Objects illuminated by the mixed light will exhibit colors closest to their original colors as perceived by eyes. Furthermore, by arranging the first and second light-emitting chips in matrix, the color rendering of the light-emitting diode module can be adjusted and improved.

Abstract: A cover with structure for facilitating hold a device enables a user to hold the device with plurality of faces stably. It can be configured to ridge a ridgeable portion and form a tubular space. The user can retain at least one finger in the space to hold the cover such that his palm can be placed more close to the center of the device to facilitate hold the device.

Abstract: A cover with structure for facilitating hold a device enables a user to hold the device with plurality of faces stably. It can be configured to ridge a ridgeable portion and form a tubular space. The user can retain at least one finger in the space to hold the cover such that his palm can be placed more close to the center of the device to facilitate hold the device.

Abstract: A method of assigning shortcut key combinations used to immediately initiate predetermined functions in a computer system, each function associated with at least one representative text. The method is characterized in that a substantial number of the assignments is each based on a numerical-shape association such that a portion of the representative text of the assigned function corresponds to at lease one of the numerical symbols of the assigned shortcut key combinations, wherein said portion does not contain any numerical symbol.

Abstract: In a decoding method and apparatus, the decoding method is used for mapping a plurality of encoding sequences to a plurality of decoding sequences, which is used by non-logographic languages. The decoding method receives an entered encoding symbol and combines the entered encoding symbol to the end of an input sequence, wherein the input sequence is temporally ambiguous such that the input sequence has possibility to be interpreted as at least two different encoding sequence combinations, each of which includes at least one of the encoding sequences.

Abstract: In a decoding method and apparatus, the decoding method is used for mapping a plurality of encoding sequences to a plurality of decoding sequences, which is used by non-logographic languages. The decoding method receives an entered encoding symbol and combines the entered encoding symbol to the end of an input sequence, wherein the input sequence is temporally ambiguous such that the input sequence has possibility to be interpreted as at least two different encoding sequence combinations, each of which includes at least one of the encoding sequences.

Abstract: An encoding method includes a mapping for mapping a plurality of encoding sequences to a plurality of decoding sequences. Each of the encoding sequences includes at least one encoding symbol chosen from an encoding symbol set. Each of the decoding sequences includes at least one decoding symbol chosen from a decoding symbol set. The encoding method is characterized in that at least one of the encoding sequences includes at least two encoding symbols, and a predetermined shape changing type of a formal symbol in the encoding sequence is denoted by a latter symbol neighboring to the formal symbol, wherein the shape changing type including at least one of shape rotating, shape mirroring, shape deflating, stroke removal, cutting and notching.

Abstract: A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column.

Abstract: A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column.

Abstract: Embodiments of the present invention are directed to a method of reducing boron outgassing at trench power IC's oxidation process for the sacrificial oxide layer whereby the threshold voltage of the power ICs can be improved and the yield of the product can be enhanced. Nitrogen is introduced into the furnace in the entire oxidation process, including the main oxidation steps. In the preparing step of ramp up, the ramp up step and the stable step, prior to the main oxidation, nitrogen is introduced in a sufficient flow rate to make the environment near the saturated vapor pressure to reduce boron outgassing at the trench.

Abstract: Embodiments of the present invention are directed to a method of reducing boron outgassing at trench power IC's oxidation process for the sacrificial oxide layer whereby the threshold voltage of the power ICs can be improved and the yield of the product can be enhanced. Nitrogen is introduced into the furnace in the entire oxidation process, including the main oxidation steps. In the preparing step of ramp up, the ramp up step and the stable step, prior to the main oxidation, nitrogen is introduced in a sufficient flow rate to make the environment near the saturated vapor pressure to reduce boron outgassing at the trench.

Abstract: The present invention provides a method of power IC inspection to inspect whether an electrically-failed portion of power ICs results from photo resist peeling before or during source implantation. First, the metal layers on the power ICs are removed by the conventional etching process, and then the dielectric layers on the power ICs are removed by the conventional etching process. Finally, the semiconductor substrate is put into an acid solution containing chromium (Cr), so that a close contour is shown at each of the power ICs whose photo resist didn't peel during photolithography process and after source implantation.

Abstract: The present invention is directed to an effective and relatively inexpensive way to measuring the depth of a well in a semiconductor device. In accordance with an aspect of the present invention, a method for measuring the depth of a well of a substrate comprises providing a substrate having a well therein and a cut through a depth of the well. The substrate is exposed to an etchant to reveal a discontinuity in a boundary at the depth of the well. The depth of the well is measured at the boundary by scanning electron microscopy (SEM) or other suitable techniques.

Abstract: The present invention is directed to an effective and relatively inexpensive way to measuring the depth of a well in a semiconductor device. In accordance with an aspect of the present invention, a method for measuring the depth of a well of a substrate comprises providing a substrate having a well therein and a cut through a depth of the well. The substrate is exposed to an etchant to reveal a discontinuity in a boundary at the depth of the well. The depth of the well is measured at the boundary by scanning electron microscopy (SEM) or other suitable techniques.

Abstract: The present invention provides a method of power IC inspection to inspect whether an electrically-failed portion of power ICs results from photo resist peeling before or during source implantation. First, the metal layers on the power ICs are removed by the conventional etching process, and then the dielectric layers on the power ICs are removed by the conventional etching process. Finally, the semiconductor substrate is put into an acid solution containing chromium (Cr), so that a close contour is shown at each of the power ICs whose photo resist didn't peel during photolithography process and after source implantation.

Abstract: A process for improving the isolation between devices of an EEPROM cell, has been developed. A high temperature anneal step is performed after an arsenic ion implantation procedure, used to create tunnel transistors for the EEPROM cell. The anneal procedure allows the high concentration of arsenic, implanted into a the top portion of a FOX region during the formation of the tunnel transistors, to be distributed throughout the FOX region, resulting in reduction in the etch rate of the FOX region, during HF containing, pre-clean procedures.