Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: A non-polarized snap-on electromagnetic relay capable of arbitrarily connecting two electrodes for electrical conduction to execute a charging or discharging operation without the need of considering positive and negative polarity includes a base, a solenoid coil assembly, a link assembly, a fixed contact assembly, and a movable contact assembly, and all these assemblies are installed on the base. The base of the electromagnetic relay further includes a barrier block disposed in the fixed contact assembly and symmetrically arranged between two fixed conductive plates, and a movable spring plate of the movable contact assembly is set across the barrier block, so that the stroke movement of the movable contact on the movable spring plate takes place on two sides of the barrier block, and the barrier block contains a strike-arc magnet.

Abstract: A computing circuit is configured to perform a bit-serial multiplication of an input signal and a weight signal. A multiplier circuit is configured to receive the input signal and the weight signal and to provide a product sum. An adder circuit is configured to receive the product sum and to provide a partial sum. A partial sum register is configured to: clock-gate a second part of the partial sum register; receive the partial sum; provide, based on the partial sum, a first output of the bit-serial multiplication through a first part of the partial sum register; determine whether not to clock-gate the second part of the partial sum register or not based on a first feature bit of the partial sum; and provide, based on the first feature bit of the partial sum, a second output of the bit-serial multiplication through the second part of the partial sum register.

Abstract: An optical fiber array includes a groove plate having a plurality of grooves disposed on a top surface thereof; and an optical component plate having a plurality of first optical components disposed on a first surface of the optical component plate and a plurality of second optical components disposed on a second surface of the optical component plate, the second surface being opposite the first surface.

Abstract: A circuit includes local computing cells. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a first data type, a first sum including (i) a first product of a first input data element and a first weight data element; and (ii) a second product of a second input data element and a second weight data element. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a second data type, (i) a second sum of a first portion of a third input data element and a first portion of a third weight data element; and (ii) a third product of a second portion of the third input data element and a second portion of the third weight data element.

Abstract: An optoelectronic device includes a first substrate, a second substrate, a photonic integrated circuit, and a laser diode. The second substrate is over the first substrate. The photonic integrated circuit is disposed on the first substrate and includes a first waveguide channel, a second waveguide channel, and a patterned structure. The first waveguide channel and the second waveguide channel are coupled to the patterned structure. The laser diode is disposed on the second substrate and configured to emit a light beam toward the patterned structure.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: A zone heater assembly of a reflow solder tool includes a gas deflector having a single-layer structure. The single-layer structure may include one or more gas-permeating patterns through which a process gas is to flow from one or more gas outlets to a gas exhaust of the zone heater assembly. The one or more gas-permeating patterns in the single-layer structure promote uniformity of gas flow through the gas exhaust and into a heating zone of the reflow solder tool. The uniformity of the gas flow of the process gas enables convection heat provided by the process gas to be uniformly distributed across the heating zone. In this way, the gas deflector described herein may decrease hot spots and/or cold spots in the heating zone, which enables greater flexibility in placement of semiconductor package substrates on a conveyor device of the reflow solder tool.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.

Abstract: Embodiment described herein provide systems, apparatuses and methods for convoluting a filter (“kernel”) to input data in the form of an input array by reusing computations of repeated data entries in the input array due to convolution movements from one convolution step to the next. In one embodiment, to compute a convolution of an input matrix and a filter matrix, instead of unrolling data entries from the input matrix of each convolution step into an input vector, only non-repeated new data entries at each convolution step may be added to the input vector. An input mapping circuit that implements an input parameter mapping matrix may then iteratively map data entries of the input vector to different weight registers that corresponds to weights in the filter matrix.

Abstract: The present invention relates to a method of cleaning relays. The method includes: a loading step by placing a relay on a feeding platform of a machine and directing a laser processing head of the machine to allow emission of laser light towards the relay; and a surface treatment step by activating the laser processing head to perform laser surface treatment on a portion of the relay to be treated. The present invention provides operators with a fast, time-saving, and efficient method for processing a large number of relays requiring surface treatment. It aims to improve upon the conventional electrolytic surface treatment techniques that are labor-intensive, time-consuming, and may have certain impacts on human health and the environment.

Abstract: An absorptive article quick decomposition system and operating method thereof is provided. The absorptive article quick decomposition system is mainly constructed by a cutting separating module, a liquid proof reclaimed material filtering module, a recycling module, a salt slurry processing module, a plastic raw material manufacturing module, a hygroscopic raw material manufacturing module, and a fluff fiber raw material manufacturing module. The absorptive article quick decomposition system and operating method make the recycled absorbent articles become possible to be decomposed into plastic raw materials, hygroscopic raw materials and fluff fiber raw materials. In addition, organic pollutants on absorbent articles are decomposed. The purified and treated water thus recovered and the recycling is realized for good.

Abstract: The present invention provides a liquid-absorbing raw material processing system and its operation method. The liquid-absorbing raw material processing system is composed of a cutting module, a bulk pulping module, a salt slurry processing module, and a liquid-absorbing raw material manufacturing module, which are connected in series. The operating method of the liquid-absorbing raw material processing system is to process absorptive articles such as diapers or sanitary napkins, etc., which are retained and made into fluff liquid-absorbing raw materials through the purification and separation steps performed by the modules of the liquid-absorbing raw material processing system.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: The present invention provides a fiber raw material processing system and its operation method. The fiber raw material processing system is composed of a cutting module, a bulk pulping module, a salt slurry processing module, a pressure screen, a separation module, an inclined screen module, and an extrusion module and a recycling module, which are connected in series. The operating method of the fiber raw material processing system is to process absorptive articles such as diapers or sanitary napkins, etc., which are retained and made into fluff fiber raw materials through the purification and separation steps performed by the modules of the fiber raw material processing system.

Abstract: A low-shrinkage photocurable material is provided in the present disclosure. The low-shrinkage photocurable material includes an acrylonitrile butadiene styrene resin, a carbon black and a dispersant. The carbon black and the dispersant are mixed with the acrylonitrile butadiene styrene resin. The weight percentage of the acrylonitrile butadiene styrene resin is 85%-99.45%, the weight percentage of the carbon black is 0.05%-5%, and the weight percentage of the dispersant is 0.5%-10%.

Abstract: A memory cell includes a write access transistor, a storage transistor, and a read access transistor. A gate of the write access transistor is connected to a write word line, a source of the write access transistor is connected to a write bit line, and a drain of the write access transistor is connected to a gate of the storage transistor. A source of the storage transistor is connected to a source line and a drain of the storage transistor is connected to a source of the read access transistor. A gate of the read access transistor is connected to a read bit line and a drain of the read access transistor is connected to read bit line. The memory cell further includes a capacitive element having a first connection to the gate of the storage transistor and a second connection to a reference voltage source.

Abstract: An integrated circuit includes a memory storage having bit cells, a write path switch configured to have a connection state determined by a reliability indicator, and a write driver having an input configured to receive an input data from a write terminal through either a first write path or a second write path. The input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. The reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.