Abstract: The present invention discloses a method for making lead-carbon electrode sheets, electrode sheet cassette and lead-carbon battery. The method includes of steps of: oxidizing lead under low-temperature atmosphere; and using a specialized ventilation method for the carbon to coat the oxidized lead. The interface layer of oxidized lead forms a stable interface between the carbon and the lead. Meanwhile, through controlling pressure and temperature, a multi-porous metal composite is formed and the porosity can be penetration paths for air and liquid when the multi-porous metal composite is applied. The lead-carbon composite is applied as a lead-carbon electrode sheet and is further welded as a lead-carbon electrode sheet of a lead-carbon battery. The lead-carbon battery carrying the lead-carbon electrode demonstrates Coulomb efficiency of 100% without heat loss on an unsaturated charge-discharge condition, demonstrating high-efficiency charging and discharging.

Abstract: A method of operating a memory device is provided, including operations: generating, based on at least one weight stored in a first memory, a weight feature to be stored in a second memory different from the first memory, wherein the weight feature is associated with a number of repetitious bits, that are in neighbor positions of and the same as a most significant bit, in the at least one weight; and accessing, according to the weight feature and an address of the at least one weight, the first memory and the second memory to transmit the at least one weight to a multiply and accumulate circuit for a first neural network layer operation.

Abstract: A circuit for data processing is provided. The circuit comprises a dual-mode adder, a max finder circuit, a zone detector circuit and an alignment circuit. The dual-mode adder generates products between first exponents of first floating point numbers and second exponents of second floating point numbers. The max finder circuit finds a maximum among first portions of the products. The zone detector circuit classify the first portions into zones by comparing the first portions and the maximum. The alignment circuit align first mantissas of the first floating point numbers according to the zones and second portions of the products to generate aligned mantissas for a floating point number operation.

Abstract: A memory device includes a memory array storing weights; a pre-charging circuit coupled to the memory array through data lines and charging, in response to a pre-charge signal, at least one data line in the data lines to a read voltage in a read operation to one in the weights; and a calibration circuit generating the pre-charge signal according to an address of the one in the weights.

Abstract: In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.

Abstract: In this disclosure, a storage circuit is provided. The storage circuit includes a gain-cell, a self-refresh unit, and a latch circuit. The gain-cell is configured to store first data in a gate of a storage transistor. The self-refresh unit is configured to read the first data from the gain-cell and write the first data back to the gain-cell. The latch circuit is configured to read the first data from the self-refresh unit and latch the first data.

Abstract: An IC device includes first and second transistors and a memory device. The first transistor includes a first source/drain (S/D) terminal coupled to a first select line, a second S/D terminal, and a gate coupled to a first word line. The second transistor includes a first S/D terminal coupled to a first bit line, a second S/D terminal, and a gate. The memory device is coupled to the second S/D terminal of the second transistor, and a first storage node includes the second S/D terminal of the first transistor and the gate of the second transistor.

Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.

Abstract: A circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third PMOS transistor coupled between the first data line and the first input terminal, a fourth PMOS transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node, and a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.

Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Abstract: An ultrasonic transducer includes a piezoceramic element with a first surface and a second surface opposite to each other through the piezoceramic element and a lateral surface connecting the first surface and the second surface, an acoustic matching layer with a third surface and a fourth surface opposite to each other through the acoustic matching layer and the third surface connecting with the second surface of the piezoceramic element, a first damping element with a fifth surface and a sixth surface opposite to each other through the first damping element and the sixth surface connecting with the first surface of the piezoceramic element, and a second damping element encapsulating the first damping element and the lateral surface of the piezoceramic element.

Abstract: An integrated circuit includes a memory storage having bit cells, a write path switch configured to have a connection state determined by a reliability indicator, and a write driver having an input configured to receive an input data from a write terminal through either a first write path or a second write path. The input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. The reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.

Abstract: A memory device is provided. The memory device includes: a write transistor, with a gate terminal connected to a write word line, and having a first source/drain terminal connected to a bit line; a storage transistor, with a gate terminal coupled to a second source/drain terminal of the write transistor to form a storage node, and having a first source/drain terminal connected to a source line; and a read transistor, with a gate terminal coupled to a read word line, and having a first source/drain terminal connected to the bit line. The read transistor and the storage transistor share a second source/drain terminal.

Abstract: A sensing method of a sense amplifier circuit is provided. The sense amplifier circuit comprises a differential amplifier. The differential amplifier comprises a first input node, a second input node, a first output node and a second output node. The sensing method comprising: providing a first switch and a second switch, wherein the first switch is coupled to the first input node and the first output node; pre-charging the first input node using a first output voltage of the first output node in response to a select signal by the first switch; and pre-charging the second input node using a second output voltage of the second output node in response to a select signal by the second switch.

Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: A non-polarized snap-on electromagnetic relay capable of arbitrarily connecting two electrodes for electrical conduction to execute a charging or discharging operation without the need of considering positive and negative polarity includes a base, a solenoid coil assembly, a link assembly, a fixed contact assembly, and a movable contact assembly, and all these assemblies are installed on the base. The base of the electromagnetic relay further includes a barrier block disposed in the fixed contact assembly and symmetrically arranged between two fixed conductive plates, and a movable spring plate of the movable contact assembly is set across the barrier block, so that the stroke movement of the movable contact on the movable spring plate takes place on two sides of the barrier block, and the barrier block contains a strike-arc magnet.

Abstract: A computing circuit is configured to perform a bit-serial multiplication of an input signal and a weight signal. A multiplier circuit is configured to receive the input signal and the weight signal and to provide a product sum. An adder circuit is configured to receive the product sum and to provide a partial sum. A partial sum register is configured to: clock-gate a second part of the partial sum register; receive the partial sum; provide, based on the partial sum, a first output of the bit-serial multiplication through a first part of the partial sum register; determine whether not to clock-gate the second part of the partial sum register or not based on a first feature bit of the partial sum; and provide, based on the first feature bit of the partial sum, a second output of the bit-serial multiplication through the second part of the partial sum register.