Patents by Inventor Jen-Yao Hsu

Jen-Yao Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9379696
    Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: June 28, 2016
    Assignee: Maxchip Electronics Corp.
    Inventors: Ming-Chi Kuo, Tsung-Chih Tsai, Jen-Yao Hsu
  • Publication number: 20150311891
    Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.
    Type: Application
    Filed: June 3, 2014
    Publication date: October 29, 2015
    Applicant: Maxchip Electronics Corp.
    Inventors: Ming-Chi Kuo, Tsung-Chih Tsai, Jen-Yao Hsu
  • Patent number: 8558177
    Abstract: An ambit light sensor with a function of IR sensing and a method of fabricating the same are provided. The ambit light sensor includes a substrate, an ambit light sensing structure, an infrared ray (IR) sensing structure, and a dielectric layer. The ambit light sensing structure is located over the substrate for sensing and filtering visible light. The IR sensing structure is located in the substrate under the ambit light sensing structure for sensing IR. The dielectric layer is located between the ambit light sensing structure and the IR sensing structure.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: October 15, 2013
    Assignee: Maxchip Electronics Corp.
    Inventors: Jin-Wei Chang, Jen-Yao Hsu, Hong-Xian Wang, Yu-Hsien Chen
  • Publication number: 20110108728
    Abstract: An ambit light sensor with a function of IR sensing and a method of fabricating the same are provided. The ambit light sensor includes a substrate, an ambit light sensing structure, an infrared ray (IR) sensing structure, and a dielectric layer. The ambit light sensing structure is located over the substrate for sensing and filtering visible light. The IR sensing structure is located in the substrate under the ambit light sensing structure for sensing IR. The dielectric layer is located between the ambit light sensing structure and the IR sensing structure.
    Type: Application
    Filed: January 28, 2010
    Publication date: May 12, 2011
    Applicant: MAXCHIP ELECTRONICS CORP.
    Inventors: Jin-Wei Chang, Jen-Yao Hsu, Hong-Xian Wang, Yu-Hsien Chen
  • Patent number: 7358567
    Abstract: A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped region. The drift region is located in the substrate under the field isolation layer and connects with the channel region and the at least one doped region. The modifying doped region is at the periphery of the at least one doped region.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: April 15, 2008
    Assignee: United Microelectronics Corp.
    Inventor: Jen-Yao Hsu
  • Patent number: 7214591
    Abstract: A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped region. The drift region is located in the substrate under the field isolation layer and connects with the channel region and the at least one doped region. The modifying doped region is at the periphery of the at least one doped region.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: May 8, 2007
    Assignee: United Microelectronics Corp.
    Inventor: Jen-Yao Hsu
  • Publication number: 20050282321
    Abstract: A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped region. The drift region is located in the substrate under the field isolation layer and connects with the channel region and the at least one doped region. The modifying doped region is at the periphery of the at least one doped region.
    Type: Application
    Filed: June 1, 2005
    Publication date: December 22, 2005
    Inventor: Jen-Yao Hsu
  • Publication number: 20050269632
    Abstract: A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped region. The drift region is located in the substrate under the field isolation layer and connects with the channel region and the at least one doped region. The modifying doped region is at the periphery of the at least one doped region.
    Type: Application
    Filed: June 7, 2004
    Publication date: December 8, 2005
    Inventor: Jen-Yao Hsu
  • Patent number: 6198148
    Abstract: A photodiode is provided comprising a substrate, a well with a first electric type within the substrate, a heavily doped region with a second electric type within the well, and a insulating layer on the substrate. The insulating layer in the position on the heavily doped region is thinner than in other positions. A junction is thus formed between the heavily doped region and the well.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: March 6, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Jen-Yao Hsu
  • Patent number: 6184050
    Abstract: A method for forming a photodiode is provided. A substrate having a well with a first electric type therein is provided. An insulating layer is formed on the substrate. The insulating layer is patterned to form an opening. The insulating layer still remains with a thin thickness below the bottom of the opening. A heavily doped region with a second electric type is formed in the well in the position below the opening. A junction is thus formed between the heavily doped region and the well.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: February 6, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Jen-Yao Hsu
  • Patent number: 6171882
    Abstract: A structure of a photo diode and a method of manufacturing a photo diode comprise the steps of providing a substrate having an isolation region and a device region. A doped region is formed adjacent to the isolation region in the substrate by performing an ion implantation step and an annealing step. Next, a protective layer utilized to prevent the plasma damage is formed on the substrate and the isolation region, and an inter-layer dielectric layer is formed on the protective layer. Thereafter, a contact hole is formed to expose a portion of the doped region by patterning the inter-layer dielectric layer and the protective layer, and a contact plug is formed by filling the contact hole with a conductive material.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: January 9, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Hung Chien, Jen-Yao Hsu, Jui-Hsiang Pan