Abstract: A TTL to CMOS input buffer integrated circuit having an input terminal for connection to an output terminal of a TTL device is disclosed.

Abstract: A resistance ladder having a plurality of resistance branches in an integrated circuit chip, including a layer of resistive material defining a plurality of discrete linear segments and a plurality of connector tabs extending from each of the linear segments at predetermined intervals for defining each resistance branch: wherein the layer of resistive material further defines a number of curvilinear segments for connecting the linear segments to provide a continuous resistive material layer for defining said resistance ladder. Each curvilinear segment is approximately a segment of a circle. The resistive material layer also defines a plurality of connector tabs extending from each curvilinear segment; with the angular separation of the tabs being approximately defined by.theta.=(R/.rho.)ln(r.sub.2,/r.sub.1),wherein R is the resistance required for each leg of the resistance ladder;.rho. is the sheet resistance of the resistive material;r.sub.1 is the inner radius of said circle; andr.sub.

Abstract: An elongated resistor is terminated in a plurality of resistance segments arranged in pairs that have mirror symmetry along a line that lies along the center line of the resistor. The pairs are coupled together and joined to metallization via contact means so that a reduced resistance contact is obtained and in which when the contact is misaligned, the resistor value is unchanged. The structure is useful in forming precision resistor ladders in integrated digital to analog converter circuits.