Abstract: A display pixel circuit having a data line loading circuit with a first capacitor, a first reset circuit coupled with the data line loading circuit, and a diode coupled to the data line loading circuit. The display pixel circuit also includes a second capacitor associated with the diode, and a second reset circuit coupled with the second capacitor. The first reset circuit is configured to reset the first capacitor. The second reset circuit is configured to reset the second capacitor, and the diode is driven by a constant current after resetting the first capacitor and the second capacitor.

Abstract: A structure and a method for reducing source line resistance of a light emitting diode. A light emitting diode display has at least a light emitting diode, a power source and a power source line structure for guiding the power source to provide the required power for driving the light emitting diode. The structure for reducing the source line resistance has an insulation layer formed on at least a part of the source line structure. The insulation layer has at least two openings exposing the source line structure. A conductive layer is formed to cover the insulation layer and is in electrical contact with the source line structure through the openings. Thereby, the conductive layer and the source line are connected in parallel, and the resistance of the source line is thus reduced.

Abstract: A display pixel circuit having a data line loading circuit with a first capacitor, a first reset circuit coupled with the data line loading circuit, and a diode coupled to the data line loading circuit. The display pixel circuit also includes a second capacitor associated with the diode, and a second reset circuit coupled with the second capacitor. The first reset circuit is configured to reset the first capacitor. The second reset circuit is configured to reset the second capacitor, and the diode is driven by a constant current after resetting the first capacitor and the second capacitor.

Abstract: A CMOS transistor is described. The CMOS transistor comprises a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a gate, a channel region, a first doped region of the first conductivity type and a source region, wherein the channel region, the first doped region and the source region are arranged along a first direction. The second TFT includes a gate, a channel region, a second doped region of the second conductivity type and a drain region, wherein the channel region, the second doped region and the drain region are arranged along the first direction. The first and the second doped regions are arranged along a second direction that is perpendicular to the first direction, and are electrically connected by a conductive line extending along the second direction.

Abstract: A CMOS transistor is described. The CMOS transistor comprises a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a gate, a channel region, a first doped region of the first conductivity type and a source region, wherein the channel region, the first doped region and the source region are arranged along a first direction. The second TFT includes a gate, a channel region, a second doped region of the second conductivity type and a drain region, wherein the channel region, the second doped region and the drain region are arranged along the first direction. The first and the second doped regions are arranged along a second direction that is perpendicular to the first direction, and are electrically connected by a conductive line extending along the second direction.

Abstract: A method is used for reducing spikes in a digital-to-analog converter (DAC), which includes a plurality of digit circuits for transforming a digital voltage signal into an analog voltage signal. The method includes receiving the digital voltage signal, setting the digit circuit corresponding to a predetermined bit of the digital voltage signal closest to an output module, and outputting an analog voltage signal corresponding to the digital voltage signal, wherein the predetermined bit of the digital voltage signal is the bit with least signal variation among the bits of the digital voltage signal.

Abstract: A method is used for reducing spikes in a digital-to-analog converter (DAC), which includes a plurality of digit circuits for transforming a digital voltage signal into an analog voltage signal. The method includes receiving the digital voltage signal,setting the digit circuit corresponding to a predetermined bit of the digital voltage signal closest to an output module, and outputting an analog voltage signal corresponding to the digital voltage signal, wherein the predetermined bit of the digital voltage signal is the bit with least signal variation among the bits of the digital voltage signal.

Abstract: A structure and a method for reducing source line resistance of a light emitting diode. A light emitting diode display has at least a light emitting diode, a power source and a power source line structure for guiding the power source to provide the required power for driving the light emitting diode. The structure for reducing the source line resistance has an insulation layer formed on at least a part of the source line structure. The insulation layer has at least two openings exposing the source line structure. A conductive layer is formed to cover the insulation layer and is in electrical contact with the source line structure through the openings. Thereby, the conductive layer and the source line are connected in parallel, and the resistance of the source line is thus reduced.