Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: A replacement method for scan cell of an integrated circuit (IC) is provided. A gate-level netlist of the IC is obtained. A place-and-route process is performed on the gate-level netlist to obtain a first netlist. A clock tree synthesis process is performed on the first netlist to obtain a second netlist. Static timing analysis is performed to analyze a plurality of first scan cells of the second netlist in normal mode and scan mode. The first scan cell is replaced with a second scan cell according to the static timing analysis that indicates the replaced first scan cell has a specific time margin in the scan mode. A first skew of the normal mode and a second skew of the scan mode are adjusted symmetrically in the first scan cell. The first skew and the second skew are adjusted asymmetrically in the second scan cell.

Abstract: A replacement method for scan cell of an integrated circuit (IC) is provided. A gate-level netlist of the IC is obtained. A place-and-route process is performed on the gate-level netlist to obtain a first netlist. A clock tree synthesis process is performed on the first netlist to obtain a second netlist. Static timing analysis is performed to analyze a plurality of first scan cells of the second netlist in normal mode and scan mode. The first scan cell is replaced with a second scan cell according to the static timing analysis that indicates the replaced first scan cell has a specific time margin in the scan mode. A first skew of the normal mode and a second skew of the scan mode are adjusted symmetrically in the first scan cell. The first skew and the second skew are adjusted asymmetrically in the second scan cell.

Abstract: A memory managing method for video data decoding process is provided. The memory managing method includes the following steps. A first frame having a first definition is stored, wherein the first frame is a first type or a second type. A second frame having the first definition is stored, wherein the second frame is the first type or the second type. A first frame having a second definition is stored in the memory space where the first frame having the first definition was originally stored, and the remaining memory space left after the original first frame having the first definition had been stored is released, wherein the memory space for storing the first frame having the first definition is greater than the memory space for storing the first frame having the second definition. A third frame having the second definition is stored, wherein the third frame is a third type.

Abstract: A method and an apparatus for decoding video image data including a plurality of frames are provided. Each of the frames includes a reserved portion and a non-reserved portion. The method comprises decoding only the non-reserved portion of one of the frames and displaying the decoded non-reserved portion of the frame and the reserved portion of a previously decoded frame. The apparatus comprises a decoding device to decode the non-reserved portion of one of the frames and a displaying device to display the reserved portion of a previously decoded frame and the decoded non-reserved portion of the frame.

Abstract: An output method for improving video image quality is provided. First, a frame data of a first frame is received, wherein the first frame may coincide with a first type or a second type. Thereafter, the first frame is subjected to a signal process step to output a processed first frame with a first standard, wherein the processed first frame comprises a first signal to noise (S/N) ratio. Next, a frame data of a second frame with a second standard is received, wherein the second frame coincides with a third type. Thereafter, a first decompression process of frame data is performed on the second frame to output a processed second frame with the first standard, wherein the processed second frame comprises a second S/N ratio. In addition, a difference between the first S/N ratio and the second S/N ratio is smaller than a predetermined minimum tolerance.

Abstract: A memory controller capable of estimating memory power consumption includes a memory control unit, a command dispatch device, plural bank state machines and a power-state and current-accumulation device. The memory control unit generates control signals based on a memory access command sent by a system for accessing a synchronous dynamic random access memory (SDRAM). The command dispatch device synchronously receives the control signals sent by the controller to the SDRAM. The plural bank state machines are connected to the command dispatch device to receive the control signals dispatched by the command dispatch device and accordingly determine whether to transfer its internal state or not. The power-state and current-accumulation device determines on which state the SDRAM is in accordance with states of the plural band state machines, thereby computing current consumption of the SDRAM.

Abstract: A data communication circuit of a SDRAM for data communication comprises a plurality of data lines coupled to a plurality of data pins. The number of the data lines, according to an embodiment of the present invention, is less than the number of the data pins. When the data communication circuit receives/outputs data, one of the LDQM pin and the UDQM pin are enabled to receive/output a first part of the data. The other LDQM pin and the UDQM pin are enabled. Accordingly, the data communication circuit of the SDRAM, according to an embodiment of the present invention, is capable of transmitting more data using a bus with a narrow width.

Abstract: A method and an apparatus for decoding video image data including a plurality of frames are provided. Each of the frames includes a reserved portion and a non-reserved portion. The method comprises decoding only the non-reserved portion of one of the frames and displaying the decoded non-reserved portion of the frame and the reserved portion of a previously decoded frame. The apparatus comprises a decoding device to decode the non-reserved portion of one of the frames and a displaying device to display the reserved portion of a previously decoded frame and the decoded non-reserved portion of the frame.

Abstract: An apparatus and a system having in-system-programming function are disclosed. The apparatus comprises a non-volatile memory, a controller and a serial interface unit. When the non-volatile memory is to be programmed, the controller will actively catch the program data from an external device via the serial interface unit and save the program data in non-volatile memory. Thus, the programming efficiency is enhanced, an additional programmer is unnecessary, and the production cost can be saved.

Abstract: A dynamic random access memory controller is suitable in controlling a first dynamic random access memory and a second dynamic random access memory, which two memory capacities are not the same. The judging circuit of the dynamic random access memory controller receives and judges whether or not a system addressing signal falls within a preset range, and outputs a judging signal. Furthermore, the transforming and shielding circuit transforms the system addressing signal and byte enable signal in accordance with the judging signal, and therefore obtains a memory addressing signal and a shielding signal for addressing the first and the second dynamic random access memories. Furthermore, the data interface circuit, in accordance with the judging signal, buffers or separates a system writing-in data signal, or, buffers or merges the memory data signal.

Abstract: A memory managing method for video data decoding process is provided. The memory managing method includes the following steps. A first frame having a first definition is stored, wherein the first frame is a first type or a second type. A second frame having the first definition is stored, wherein the second frame is the first type or the second type. A first frame having a second definition is stored in the memory space where the first frame having the first definition was originally stored, and the remaining memory space left after the original first frame having the first definition had been stored is released, wherein the memory space for storing the first frame having the first definition is greater than the memory space for storing the first frame having the second definition. A third frame having the second definition is stored, wherein the third frame is a third type.

Abstract: An output method for improving video image quality is provided. First, a frame data of a first frame is received, wherein the first frame may coincide with a first type or a second type. Thereafter, the first frame is subjected to a signal process step to output a processed first frame with a first standard, wherein the processed first frame comprises a first signal to noise (S/N) ratio. Next, a frame data of a second frame with a second standard is received, wherein the second frame coincides with a third type. Thereafter, a first decompression process of frame data is performed on the second frame to output a processed second frame with the first standard, wherein the processed second frame comprises a second S/N ratio. In addition, a difference between the first S/N ratio and the second S/N ratio is smaller than a predetermined minimum tolerance.

Abstract: A data communication circuit of a SDRAM for data communication comprises a plurality of data lines coupled to a plurality of data pins. The number of the data lines, according to an embodiment of the present invention, is less than the number of the data pins. When the data communication circuit receives/outputs data, one of the LDQM pin and the UDQM pin are enabled to receive/output a first part of the data. The other LDQM pin and the UDQM pin are enabled. Accordingly, the data communication circuit of the SDRAM, according to an embodiment of the present invention, is capable of transmitting more data using a bus with a narrow width.

Abstract: A memory controller capable of estimating memory power consumption includes a memory control unit, a command dispatch device, plural bank state machines and a power-state and current-accumulation device. The memory control unit generates control signals based on a memory access command sent by a system for accessing a synchronous dynamic random access memory (SDRAM). The command dispatch device synchronously receives the control signals sent by the controller to the SDRAM. The plural bank state machines are connected to the command dispatch device to receive the control signals dispatched by the command dispatch device and accordingly determine whether to transfer its internal state or not. The power-state and current-accumulation device determines on which state the SDRAM is in accordance with states of the plural band state machines, thereby computing current consumption of the SDRAM.

Abstract: An architecture for video decompressor to efficiently access synchronously memory includes a synchronous memory device having an A-bank and B-bank for being stored with image data, and a memory controller for controlling data access to the synchronous memory to perform motion compensation and display. The image data has a plurality of scan lines and every four scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (4N+0)-th and (4N+1)-th scan lines, and the B-bank is sequentially stored with the (4N+2)-th and (4N+3)-th scan lines, where N is a non-negative integer, so as to always perform memory operations by alternately accessing the A-bank and B-bank.