Patents by Inventor Jeng Chang HER
Jeng Chang HER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021474Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.Type: ApplicationFiled: July 31, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Lid.Inventors: Yun-Yu HSIEH, Ying Ting HSIA, Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU
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Patent number: 11776847Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.Type: GrantFiled: August 9, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 11232978Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.Type: GrantFiled: April 10, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Publication number: 20210366770Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 11088025Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.Type: GrantFiled: May 26, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Publication number: 20200286781Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Yu HSIEH, Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
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Publication number: 20200243378Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 10679896Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.Type: GrantFiled: September 24, 2018Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 10651079Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.Type: GrantFiled: December 17, 2018Date of Patent: May 12, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTUING CO., LTD.Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Publication number: 20190139822Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.Type: ApplicationFiled: December 17, 2018Publication date: May 9, 2019Inventors: Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
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Publication number: 20190088542Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.Type: ApplicationFiled: September 24, 2018Publication date: March 21, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 10157782Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.Type: GrantFiled: January 24, 2018Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 10083863Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.Type: GrantFiled: August 23, 2017Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Publication number: 20180166332Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.Type: ApplicationFiled: January 24, 2018Publication date: June 14, 2018Inventors: Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
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Patent number: 9905456Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.Type: GrantFiled: September 26, 2016Date of Patent: February 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 9691809Abstract: Disclosed is a method of fabricating an image sensor device, such as a BSI image sensor, and more particularly, a method of forming a dielectric film in a radiation-absorption region without using a conventional plasma etching causing roughness on the surface and non-uniformity within a die and a wafer. The method includes providing layers comprising a substrate having radiation sensors adjacent its front surface, an anti-reflective layer formed over the back surface of the substrate, a sacrificial dielectric layer formed over the anti-reflective layer, and a conductive layer formed over the sacrificial dielectric layer in a radiation-blocking region. The method further includes removing the sacrificial dielectric layer in the radiation-absorption region completely by a highly selective etching process and forming a dielectric film on the anti-reflective layer by deposition such as CVD or PVD while precisely controlling the thickness.Type: GrantFiled: June 28, 2013Date of Patent: June 27, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng Chang Her, Hung Jui Chang, Li Te Hsu, Chung-Bin Tseng
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Patent number: 9484207Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.Type: GrantFiled: May 30, 2014Date of Patent: November 1, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jeng-Chang Her, Chia-Cheng Lin, Hung-Jui Chang, Yu-Sheng Su, Shu-Huei Suen
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Publication number: 20150348838Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Jeng-Chang HER, Chia-Cheng LIN, Hung-Jui CHANG, Yu-Sheng SU, Shu-Huei SUEN
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Publication number: 20140263958Abstract: Disclosed is a method of fabricating an image sensor device, such as a BSI image sensor, and more particularly, a method of forming a dielectric film in a radiation-absorption region without using a conventional plasma etching causing roughness on the surface and non-uniformity within a die and a wafer. The method includes providing layers comprising a substrate having radiation sensors adjacent its front surface, an anti-reflective layer formed over the back surface of the substrate, a sacrificial dielectric layer formed over the anti-reflective layer, and a conductive layer formed over the sacrificial dielectric layer in a radiation-blocking region. The method further includes removing the sacrificial dielectric layer in the radiation-absorption region completely by a highly selective etching process and forming a dielectric film on the anti-reflective layer by deposition such as CVD or PVD while precisely controlling the thickness.Type: ApplicationFiled: June 28, 2013Publication date: September 18, 2014Inventors: Jeng Chang Her, Hung Jui Chang, Li Te Hsu, Chung-Bin Tseng
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Publication number: 20100240220Abstract: A process of stripping a patterned photoresist layer and removing a dielectric liner includes performing an oxygen-containing plasma dry etch process and performing a fluorine-containing plasma dry etch process in the same reaction chamber at a process temperature less than 120° C.Type: ApplicationFiled: March 11, 2010Publication date: September 23, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wei CHIU, Yih Song CHIU, Tzu Chan WENG, Jeng Chang HER