Patents by Inventor Jeng-Cheng Liu

Jeng-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10535696
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Shuang-Ji Tsai, Yueh-Chiou Lin
  • Publication number: 20190244999
    Abstract: An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • Publication number: 20190172857
    Abstract: An image sensor includes a substrate having a pixel region and a periphery region. The image sensor further includes a first isolation structure formed in the pixel region; the first isolation structure including a first trench having a first depth. The image sensor further includes a second isolation structure formed in the periphery region; the second isolation structure including a second trench having a second depth greater than the first depth.
    Type: Application
    Filed: January 28, 2019
    Publication date: June 6, 2019
    Inventors: Jeng-Shyan LIN, Dun-Nian YAUNG, Jen-Cheng LIU, Chun-Chieh CHUANG, Volume CHIEN
  • Publication number: 20190148435
    Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Patent number: 10290671
    Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • Patent number: 10154559
    Abstract: A control circuit includes a first control unit, a power unit, a driver unit, a second control unit, a power source, a first switch, a pull-up element and a second switch. The first control unit is used to detect whether a configuration channel line has a predetermined divided voltage and generate a control signal accordingly. The power unit is coupled to the configuration channel line and a power line for supplying power to the driver unit. The driver unit is used to enable or disable a light emitting unit according to the control signal. The second control unit is used to detect whether the configuration channel line has the predetermined divided voltage and control the first switch and the second switch accordingly. The first switch is coupled between a power source and the configuration channel line. The second switch is coupled between the pull-up element and the configuration channel line.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 11, 2018
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventors: Chih-Sheng Yang, Jeng-Cheng Liu
  • Patent number: 7042049
    Abstract: A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: May 9, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lain-Jong Li, Tien-I Bao, Shwang-Ming Jeng, Syun-Ming Jang, Jun-Lung Huang, Jeng-Cheng Liu
  • Publication number: 20040191977
    Abstract: A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.
    Type: Application
    Filed: April 13, 2004
    Publication date: September 30, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Lain-Jong Li, Tien-I Bao, Shwang-Ming Jeng, Syun-Ming Jang, Jun-Lung Huang, Jeng-Cheng Liu
  • Patent number: 6753260
    Abstract: A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: June 22, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Lain-Jong Li, Tien-I Bao, Shwang-Ming Jeng, Syun-Ming Jang, Jun-Lung Huang, Jeng-Cheng Liu