Patents by Inventor Jeng Gong
Jeng Gong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130277718Abstract: A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wing Chor Chan, Chih Min Hu, Jeng Gong
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Patent number: 8557653Abstract: A method of manufacturing a junction-field-effect-transistor (JFET) device, the method includes the steps of providing a substrate of a first-type impurity; forming a first well region of a second-type impurity in the substrate; forming a second well region and a third well region of the first-type impurity separated from each other in the first well region; forming a fourth well region of the first-type impurity between the second well region and the third well region; forming a first diffused region of the second-type impurity between the second well region and the fourth well region; forming a second diffused region of the second-type impurity between the third well region and the fourth well region; forming a pair of first doped regions of the second-type impurity in the first well region, and a pair of second doped regions of the first-type impurity in the second well region and the third well region respectively; forming a third doped region of the second-type impurity in the first well region between tType: GrantFiled: December 12, 2012Date of Patent: October 15, 2013Assignee: Macronix International Co., Ltd.Inventors: Chih-Min Hu, Chung Yu Hung, Wing Chor Chan, Jeng Gong
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Patent number: 8350304Abstract: A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.Type: GrantFiled: June 7, 2010Date of Patent: January 8, 2013Assignee: Macronix International Co., Ltd.Inventors: Chih-Min Hu, Chung Yu Hung, Wing Chor Chan, Jeng Gong
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Patent number: 8264056Abstract: A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced.Type: GrantFiled: July 29, 2010Date of Patent: September 11, 2012Assignee: Macronix International Co., Ltd.Inventors: Chung Yu Hung, Chih Min Hu, Wing Chor Chan, Jeng Gong
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Publication number: 20120205778Abstract: The present invention relates to a package structure and method for manufacturing the same. The package structure can minimize the area of the circuit board used for packaging, by stacking a passive element directly on a chip. The disclosed package structure comprises: a circuit board having a first surface, where a plurality of first connecting pads being disposed thereon; a chip unit having an active surface, a non-active surface and a plurality of conductive vias, while a plurality of second connecting pads and a plurality of electric pads being disposed on the active surface, and a plurality of third connecting pads being disposed on the non-active surface; a plurality of solder balls electrically connected with the first connecting pads and the second connecting pads; and a passive element being electrically connected with the third connecting pads. The passive element and the chip unit both electrically connect to the chip unit.Type: ApplicationFiled: May 19, 2011Publication date: August 16, 2012Inventors: Yuan-Tai LAI, Jeng-Gong DUH, Yu-Huei LEE, Ke-Horng CHEN, Kang SHENG, Tsung-Chan WU
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Publication number: 20120181653Abstract: The present invention discloses a semiconductor PN junction structure and a manufacturing method thereof. From top view, the PN junction includes a staggered comb-teeth structure. The PN junction forms a depletion region with enhanced breakdown voltage, hence broadening the applications of a semiconductor device having such PN junction.Type: ApplicationFiled: January 13, 2011Publication date: July 19, 2012Inventors: TSUNG-YI HUANG, Hung-Der Su, Kuo-Cheng Chang, Chun-Yi Hung, Kuo-Hsuan Lo, Jeng Gong
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Publication number: 20120168868Abstract: A field-effect transistor has an extra gate above a shallow trench isolation (STI) to enhance and to adapt the low-frequency noise induced by an STI-silicon interface. By changing the voltage applied to the STI gate, the field-effect transistor is able to adapt its low-frequency noise over four decades. The field-effect transistor can be fabricated with a standard CMOS logic process without additional masks or process modification.Type: ApplicationFiled: November 18, 2011Publication date: July 5, 2012Inventors: Tang-Jung CHIU, Jeng GONG, Hsin CHEN
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Patent number: 8158475Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.Type: GrantFiled: September 10, 2010Date of Patent: April 17, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chun-Lin Tsai, Chien-Chih Chou
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Patent number: 8159029Abstract: A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.Type: GrantFiled: October 22, 2008Date of Patent: April 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chun-Lin Tsai, Chien-Chih Chou
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Publication number: 20120025278Abstract: A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced.Type: ApplicationFiled: July 29, 2010Publication date: February 2, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung Yu Hung, Chih Min Hu, Wing Chor Chan, Jeng Gong
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Publication number: 20110291187Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Inventors: Wing Chor Chan, Chih-Min Hu, Shyi-Yuan Wu, Jeng Gong
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Publication number: 20110220973Abstract: A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.Type: ApplicationFiled: June 7, 2010Publication date: September 15, 2011Inventors: Chih-Min HU, Chung Yu HUNG, Wing Chor CHAN, Jeng GONG
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Publication number: 20110147950Abstract: The present invention discloses a metallization layer structure for flip chip package, which comprises an UBM layer formed on a metal pad, whereby a fine-quality tin-based solder ball can be formed on the metal pad. The UBM layer is a NiZnP layer formed via the reduction and oxidization of a solution containing nickel sulfate (Ni2SO4), zinc sulfate (ZnSO4), sodium dihydrogen phosphite (NaH2PO2), sodium citrate dihydrate (Na3C6H5O7-2H2O), and ammonium chloride (NH4Cl). The present invention replaces the conventional Au/Ni—P dual-layer structure. Therefore, the present invention can decrease the complexity of the process and reduce the cost. Further, the metallization layer structure of the present invention is tough, hard to peel off and highly corrosion-resistant.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Inventors: Fong-Cheng Tai, Chi-Yang Yu, Jeng-Gong Duh
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Publication number: 20110008944Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.Type: ApplicationFiled: September 10, 2010Publication date: January 13, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chun-Lin Tsai, Chien-Chih Chou
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Patent number: 7816744Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.Type: GrantFiled: July 9, 2008Date of Patent: October 19, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chun-Lin Tsai, Chien-Chih Chou
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Patent number: 7714663Abstract: A cascode low noise amplifier includes an input transistor and an output transistor cascode together, the input transistor has a source coupled to an active inductor, and the output transistor has a drain to provide an output signal. By using the active inductor, the low noise amplifier has smaller size, lower noise figure, and higher gain. The active inductor also provides input impedance matching for the low noise amplifier.Type: GrantFiled: October 24, 2007Date of Patent: May 11, 2010Assignee: National Tsing Hua UniversityInventors: Jeng Gong, I-Lun Huang
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Publication number: 20100096697Abstract: A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.Type: ApplicationFiled: October 22, 2008Publication date: April 22, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Yi Su, Pou-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chun Lin Tsai, Chien-Chih Chou
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Publication number: 20100006934Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.Type: ApplicationFiled: July 9, 2008Publication date: January 14, 2010Inventors: Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chun-Lin Tsai, Chien-Chih Chou
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Publication number: 20090051000Abstract: A semiconductor device structure is provided. By placing an insulating dielectric material in the drift region of a device to modulate the electric field distribution and current flow in the drift region, the breakdown voltage of the device is increased while the turn-on impedance of the device is reduced.Type: ApplicationFiled: August 20, 2008Publication date: February 26, 2009Inventors: JENG GONG, Wen-Chun Chung, Ru-Yi Su, Fu-Hsiung Yang
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Publication number: 20080111632Abstract: A cascode low noise amplifier includes an input transistor and an output transistor cascode together, the input transistor has a source coupled to an active inductor, and the output transistor has a drain to provide an output signal. By using the active inductor, the low noise amplifier has smaller size, lower noise figure, and higher gain. The active inductor also provides input impedance matching for the low noise amplifier.Type: ApplicationFiled: October 24, 2007Publication date: May 15, 2008Inventors: Jeng Gong, I-Lun Huang