Patents by Inventor Jeng-Horng Chen
Jeng-Horng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921434Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.Type: GrantFiled: December 15, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 11914286Abstract: The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.Type: GrantFiled: April 4, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Amo Chen, Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Chih-Cheng Lin, Jeng-Horng Chen
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Patent number: 11740563Abstract: A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.Type: GrantFiled: February 22, 2022Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20230124211Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20220229360Abstract: The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: AMO CHEN, YUN-YUE LIN, TA-CHENG LIEN, HSIN-CHANG LEE, CHIH-CHENG LIN, JENG-HORNG CHEN
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Patent number: 11378894Abstract: The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.Type: GrantFiled: October 28, 2019Date of Patent: July 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Chieh Chien, Jeng-Horng Chen, Jui-Ching Wu, Chia-Chen Chen, Hung-Chang Hsieh, Chi-Lun Lu, Chia-Hao Yu, Shih-Ming Chang, Anthony Yen
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Publication number: 20220179326Abstract: A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 11294274Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a porous pellicle frame, a mask with a patterned surface, a first thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame, and a second thermal conductive adhesive layer that secures the porous pellicle frame to the mask.Type: GrantFiled: January 13, 2020Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Amo Chen, Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Chih-Cheng Lin, Jeng-Horng Chen
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Patent number: 11256179Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: GrantFiled: October 22, 2019Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 11086227Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.Type: GrantFiled: June 12, 2020Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
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Patent number: 11073755Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.Type: GrantFiled: August 17, 2020Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
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Patent number: 11003069Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.Type: GrantFiled: May 4, 2020Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Yu, Chi-Lun Lu, Chih-Tsung Shih, Ching-Wei Shen, Jeng-Horng Chen
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Patent number: 10976672Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: GrantFiled: April 29, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
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Extreme ultraviolet lithography system, device, and method for printing low pattern density features
Patent number: 10976655Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.Type: GrantFiled: June 22, 2020Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen -
Publication number: 20200379335Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
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Patent number: 10831094Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.Type: GrantFiled: October 18, 2019Date of Patent: November 10, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
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Patent number: 10825684Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a multi-metal complex including an extreme ultraviolet (EUV) absorption element and a bridging element. By way of example, the EUV absorption element includes a first metal type and the bridging element includes a second metal type. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.Type: GrantFiled: January 6, 2017Date of Patent: November 3, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Hao Chang, Chien-Chih Chen, Kuo-Chang Kau, Jeng-Horng Chen, Pi-Yeh Chia, Chi-Ren Chen, Ying-Chih Lin
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Extreme Ultraviolet Lithography System, Device, and Method for Printing Low Pattern Density Features
Publication number: 20200319545Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen -
Publication number: 20200310250Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.Type: ApplicationFiled: June 12, 2020Publication date: October 1, 2020Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
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Publication number: 20200264503Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Chia-Hao Yu, Chi-Lun Lu, Chih-Tsung Shih, Ching-Wei Shen, Jeng-Horng Chen