Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: A method of managing data access of a storage medium includes establishing an address mapping table to record a physical address of a first data stored in the storage medium, where the physical address of the first data is mapped to a logical address of the first data; and when receiving a command for handling the first data stored in the storage medium internally, processing the address mapping table to serve the command without physically accessing the first data stored in the storage medium.

Abstract: A method of managing data access of a storage medium includes establishing an address mapping table to record a physical address of a first data stored in the storage medium, where the physical address of the first data is mapped to a logical address of the first data; and when receiving a command for handling the first data stored in the storage medium internally, processing the address mapping table to serve the command without physically accessing the first data stored in the storage medium.

Abstract: A driving circuit includes: a first reference current source injects a reference current; each first switch unit is coupled between the first reference current source and one of first and second output ports; a second reference current source sinks the reference current; each second switch unit is coupled between the second reference current source and one of the output ports; a load unit is coupled between the output ports, and a common voltage is applied onto the load unit; and a calibration module calibrates an impedance of the load unit according to a voltage at one of the output ports, and the voltage is generated due to the reference current passing through one of the first switch units, the load unit, and one of the second switch units.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_OK primitive (reception with no error primitive) and sets a error flag to report to the application layer of the receiver to eliminate the interference.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_OK primitive (reception with no error primitive) and sets a error flag to report to the application layer of the receiver to eliminate the interference.

Abstract: A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.

Abstract: A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode.

Abstract: The application discloses methods applied to an electronic system capable of operating in a non power saving mode and a power saving mode. According to one of the methods, the idle time when the electronic system is idle in the non-power saving mode is measured. If the idle time equals or exceeds a mode entry time, the electronic system enters the power saving mode. The power down duration when the electronic system stays in the power saving mode is measured. The mode entry time is then modified based upon the power down duration.

Abstract: A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode.

Abstract: An electronic device comprises an interface unit, a control circuit and a microprocessor. The interface unit receives a first operational firmware from a host. The control circuit transfers the first operational firmware to a memory. The microprocessor executes the first operational firmware which stored in the memory. The microprocessor controls operations of the electronic device according to the first operational firmware. And the control circuit is electrically coupled to a non-volatile memory which stores a second operational firmware for performing a specific function also performed by the first operational firmware.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.

Abstract: A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.

Abstract: A peripheral device for receiving a data frame containing control information from a serial transmission channel is disclosed. The peripheral device includes an information interpreter and a control unit. The information interpreter is coupled to the serial transmission channel, and used for receiving the data frame and interpreting the data frame to generate an operation signal according to the control information. The control unit is coupled to the information interpreter, and used for receiving the operation signal to execute an operation according to the control information.

Abstract: An optical disc drive includes a microprocessor, a control IC, an RF IC, and an interface unit. The microprocessor is electrically coupled to the control IC. The control IC is electrically coupled to the RF IC, a volatile RAM, an optional non-volatile ROM, and to a bus interface for communications with an external host. The interface unit is electrically coupled to the bus interface. Initialization of the optical disc drive is performed using initialization data stored in a non-volatile manner in the ROM, if present, or downloaded from the host if the ROM is not present. After the initialization, the interface unit signals an application program in the host to download the optical drive's operational firmware and writes received data into the RAM. The microprocessor is initialized with the operational firmware's starting address and the microprocessor executes the downloaded operational firmware. The ROM may also store read operation firmware to enable the optical disc drive to read data stored in the disc.

Abstract: An optical disc drive includes a microprocessor, a control IC, an RF IC, and an interface unit. The microprocessor is electrically coupled to the control IC. The control IC is electrically coupled to the RF IC, a volatile RAM, an optional non-volatile ROM, and to a bus interface for communications with an external host. The interface unit is electrically coupled to the bus interface. Initialization of the optical disc drive is performed using initialization data stored in a non-volatile manner in the ROM, if present, or downloaded from the host if the ROM is not present. After the initialization, the interface unit signals an application program in the host to download the optical drive's operational firmware and writes received data into the RAM. The microprocessor is initialized with the operational firmware's starting address and the microprocessor executes the downloaded operational firmware.