Patents by Inventor Jeng-Hua Wei
Jeng-Hua Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11844288Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an upper electrode and a magnetic tunnel junction. The magnetic tunnel junction is disposed between the heavy metal layer and the upper electrode. The magnetic tunnel junction includes a free layer and a pinned layer. The free layer is disposed on the heavy metal layer, and the free layer has a first film plane area. The pinned layer is disposed on the free layer, and the pinned layer has a second film plane area. There is a preset angle between a long axis direction of a film plane shape of the free layer and a long axis direction of a film plane shape of the pinned layer, and the first film plane area is larger than the second film plane area.Type: GrantFiled: February 4, 2021Date of Patent: December 12, 2023Assignee: Industrial Technology Research InstituteInventors: Hsin-Han Lee, Jeng-Hua Wei, I-Jung Wang, Shan-Yi Yang, Yao-Jen Chang
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Patent number: 11758821Abstract: A magnetic memory structure includes a heavy-metal layer, a plurality of magnetic tunneling junction (MTJ) layer, a conductive layer and an insulation layer. In an example, the pinned-layer of the MTJ layers are arranged in a string form and disposed over the barrier-layer. In an example also disclosed, the pinned-layer, the free-layer of the MTJ layers are arranged in a string form. Whereas the pinned-layers are disposed over the barrier-layer and the free-layers are disposed over the heavy-metal layer. The conductive layer is formed under the heavy-metal layer and includes a first conductive portion and a second conductive portion separated from each other and connected with two end of the heavy-metal layer respectively. The insulation layer fills up an interval between the first conductive portion and the second conductive portion. The conductive layer has an electric conductivity higher than that of the heavy-metal layer.Type: GrantFiled: December 8, 2021Date of Patent: September 12, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ziaur Rahaman Shakh, I-Jung Wang, Jeng-Hua Wei
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Publication number: 20230178130Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an antiferromagnetic layer, and a magnetic tunnel junction. The antiferromagnetic layer is disposed on the heavy metal layer, and the magnetic tunnel junction is disposed on the antiferromagnetic layer. The magnetic tunnel junction includes a free layer, a barrier layer, and a pinned layer. The barrier layer is disposed on the free layer, and the pinned layer is disposed on the barrier layer. A film surface shape of the free layer is a rounded rectangle.Type: ApplicationFiled: December 28, 2021Publication date: June 8, 2023Applicant: Industrial Technology Research InstituteInventors: Hsin-Han Lee, Jeng-Hua Wei, I-Jung Wang, Shan-Yi Yang, Yao-Jen Chang, Fang-Ming Chen
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Patent number: 11625588Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.Type: GrantFiled: March 4, 2020Date of Patent: April 11, 2023Assignee: Industrial Technology Research InstituteInventors: Tuo-Hung Hou, Shyh-Shyuan Sheu, Jeng-Hua Wei, Heng-Yuan Lee, Ming-Hung Wu
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Publication number: 20220109100Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an upper electrode and a magnetic tunnel junction. The magnetic tunnel junction is disposed between the heavy metal layer and the upper electrode. The magnetic tunnel junction includes a free layer and a pinned layer. The free layer is disposed on the heavy metal layer, and the free layer has a first film plane area. The pinned layer is disposed on the free layer, and the pinned layer has a second film plane area. There is a preset angle between a long axis direction of a film plane shape of the free layer and a long axis direction of a film plane shape of the pinned layer, and the first film plane area is larger than the second film plane area.Type: ApplicationFiled: February 4, 2021Publication date: April 7, 2022Applicant: Industrial Technology Research InstituteInventors: Hsin-Han Lee, Jeng-Hua Wei, I-Jung Wang, Shan-Yi Yang, Yao-Jen Chang
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Publication number: 20220102623Abstract: A magnetic memory structure includes a heavy-metal layer, a plurality of magnetic tunneling junction (MTJ) layer, a conductive layer and an insulation layer. In an example, the pinned-layer of the MTJ layers are arranged in a string form and disposed over the barrier-layer. In an example also disclosed, the pinned-layer, the free-layer of the MTJ layers are arranged in a string form. Whereas the pinned-layers are disposed over the barrier-layer and the free-layers are disposed over the heavy-metal layer. The conductive layer is formed under the heavy-metal layer and includes a first conductive portion and a second conductive portion separated from each other and connected with two end of the heavy-metal layer respectively. The insulation layer fills up an interval between the first conductive portion and the second conductive portion. The conductive layer has an electric conductivity higher than that of the heavy-metal layer.Type: ApplicationFiled: December 8, 2021Publication date: March 31, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ziaur Rahaman Shakh, I-Jung Wang, Jeng-Hua Wei
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Patent number: 11227990Abstract: A magnetic memory structure is provided. The magnetic memory structure includes a magnetic tunneling junction (MTJ) layer and a heavy-metal layer. The MTJ layer includes a pinned-layer, a barrier-layer formed under the pinned-layer and a free-layer formed under the barrier-layer. The heavy-metal layer is formed under the free-layer. The barrier-layer has a first upper surface, the pinned-layer has a lower surface, and area of the first upper surface is larger than area of the lower surface.Type: GrantFiled: July 17, 2019Date of Patent: January 18, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ziaur Rahaman Shakh, I-Jung Wang, Jeng-Hua Wei
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Publication number: 20210150317Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.Type: ApplicationFiled: March 4, 2020Publication date: May 20, 2021Applicant: Industrial Technology Research InstituteInventors: Tuo-Hung Hou, Shyh-Shyuan Sheu, Jeng-Hua Wei, Heng-Yuan Lee, Ming-Hung Wu
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Publication number: 20210020827Abstract: A magnetic memory structure is provided. The magnetic memory structure includes a magnetic tunneling junction (MTJ) layer and a heavy-metal layer. The MTJ layer includes a pinned-layer, a barrier-layer formed under the pinned-layer and a free-layer formed under the barrier-layer. The heavy-metal layer is formed under the free-layer. The barrier-layer has a first upper surface, the pinned-layer has a lower surface, and area of the first upper surface is larger than area of the lower surface.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ziaur Rahaman Shakh, I-Jung Wang, Jeng-Hua Wei
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Patent number: 10784441Abstract: A perpendicularly magnetized spin-orbit magnetic device including a heavy metal layer, a magnetic tunnel junction, a first antiferromagnetic layer, a first block layer and a first stray field applying layer is provided. The magnetic tunnel junction is disposed on the heavy metal layer. The first block layer is disposed between the magnetic tunnel junction and the first antiferromagnetic layer. The first stray field applying layer is disposed between the first antiferromagnetic layer and the first block layer. The magnetic tunnel junction comprises a free layer, a tunneling barrier layer, and pinned layer. The tunneling barrier layer is disposed on the free layer. The pinned layer is disposed on the tunneling barrier layer. A film plane area of the free layer is greater than a film plane area of the tunneling barrier layer and a film plane area of the pinned layer.Type: GrantFiled: October 28, 2019Date of Patent: September 22, 2020Assignee: Industrial Technology Research InstituteInventors: Hsin-Han Lee, Shan-Yi Yang, Yao-Jen Chang, I-Jung Wang, Jeng-Hua Wei
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Publication number: 20200058847Abstract: A perpendicularly magnetized spin-orbit magnetic device including a heavy metal layer, a magnetic tunnel junction, a first antiferromagnetic layer, a first block layer and a first stray field applying layer is provided. The magnetic tunnel junction is disposed on the heavy metal layer. The first block layer is disposed between the magnetic tunnel junction and the first antiferromagnetic layer. The first stray field applying layer is disposed between the first antiferromagnetic layer and the first block layer. The magnetic tunnel junction comprises a free layer, a tunneling barrier layer, and pinned layer. The tunneling barrier layer is disposed on the free layer. The pinned layer is disposed on the tunneling barrier layer. A film plane area of the free layer is greater than a film plane area of the tunneling barrier layer and a film plane area of the pinned layer.Type: ApplicationFiled: October 28, 2019Publication date: February 20, 2020Applicant: Industrial Technology Research InstituteInventors: Hsin-Han Lee, Shan-Yi Yang, Yao-Jen Chang, I-Jung Wang, Jeng-Hua Wei
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Patent number: 8283469Abstract: The present invention discloses a soluble and air-stable perylene diimide (PDI) derivative to function as an N-type organic semiconductor material. In the PDI derivative of the present invention, the core thereof is substituted by electron withdrawing groups, and the side chains thereof are substituted by benzene functional groups, whereby are promoted the solubility and air-stability of the molecule. The PDI derivative of the present invention can be used to fabricate an organic semiconductor element via a soluble process at a low temperature and under an atmospheric environment.Type: GrantFiled: March 24, 2010Date of Patent: October 9, 2012Assignee: National Tsing Hua UniversityInventors: Szu-Ying Chen, Heng-Wen Ting, Tri-Rung Yew, Jeng-Hua Wei
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Publication number: 20110233526Abstract: The present invention discloses a soluble and air-stable perylene diimide (PDI) derivative to function as an N-type organic semiconductor material. In the PDI derivative of the present invention, the core thereof is substituted by electron withdrawing groups, and the side chains thereof are substituted by benzene functional groups, whereby are promoted the solubility and air-stability of the molecule. The PDI derivative of the present invention can be used to fabricate an organic semiconductor element via a soluble process at a low temperature and under an atmospheric environment.Type: ApplicationFiled: March 24, 2010Publication date: September 29, 2011Inventors: Szu-Ying Chen, Heng-Wen Ting, Tri-Rung Yew, Jeng-Hua Wei
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Patent number: 7535081Abstract: A metal nanoline process and applications on growth of aligned nanostructures thereof. A nano-structure is provided with a substrate with at least one nanodimensional metal catalyst line disposed thereon and at least one carbon nanotube or silicon nanowire extending along an end of the metal catalyst line.Type: GrantFiled: October 21, 2004Date of Patent: May 19, 2009Assignee: Industrial Technology Research InstituteInventors: Ming-Jiunn Lai, Jeng-Hua Wei, Hung-Hsiang Wang, Po-Yuan Lo, Ming-Jer Kao
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Publication number: 20070155064Abstract: A method for manufacturing a carbon nano-tube field-effect transistor (CNT-FET), comprising steps of: forming a patterned conductive layer on a substrate; forming a dielectric layer covering the conductive layer and the substrate; forming a carbon nano-tube layer between a pair of electrodes on the dielectric layer; and performing a treatment process on the carbon nano-tube layer so that the carbon nano-tube layer is semiconducting.Type: ApplicationFiled: May 10, 2006Publication date: July 5, 2007Inventors: Bae-Horng Chen, Jeng-Hua Wei, Po-Yuan Lo, Zing-Way Pei
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Patent number: 7182914Abstract: The present invention relates to a structure and manufacturing process of a nano device transistor for a biosensor. The structure, the manufacturing process and the related circuit for a carbon nano tube or nano wire transistor biosensor device are provided. The refurbished nano device is used for absorbing various anti-bodies so as to detect the specific antigens or absorbing various biotins. Therefore, the object of the present invention to detect the specific species for bio measurement can be achieved.Type: GrantFiled: November 26, 2003Date of Patent: February 27, 2007Assignee: Industrial Technology Research InstituteInventors: Ming-Jiunn Lai, Hung-Hsiang Wang, Jeng-Hua Wei, Hsin-Hui Chen, Ming-Jer Kao
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Patent number: 7001805Abstract: A method for fabricating an n-type carbon nanotube device, characterized in that thermal annealing and plasma-enhanced chemical vapor-phased deposition (PECVD) are employed to form a non-oxide gate layer on a carbon nanotube device. Moreover, the inherently p-type carbon nanotube can be used to fabricate an n-type carbon nanotube device with reliable device characteristics and high manufacturing compatibility.Type: GrantFiled: September 4, 2002Date of Patent: February 21, 2006Assignee: Industrial Technology Research InstituteInventors: Hung-Hsiang Wang, Jeng-Hua Wei, Ming-Jer Kao
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Publication number: 20050287788Abstract: This specification discloses a manufacturing method of nanowire array. The method includes the steps of: providing a substrate; forming an insulating layer on the substrate; forming a metal catalyst layer on the insulating layer by spin on glass (SOG), the metal catalyst being Au, Ag, or Pt; forming a covering layer on the metal catalyst layer by SOG; patternizing the covering layer exposed out of the metal catalyst layer; etching the exposed metal catalyst layer to form a patternized metal catalyst layer; and forming a plurality of nanowires in the patternized metal catalyst layer.Type: ApplicationFiled: August 9, 2004Publication date: December 29, 2005Applicant: Industrial Technology Research InstituteInventors: Jeng-Hua Wei, Hung-Hsiang Wang, Po-Yuan Lo, Ming-Jer Kao
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Patent number: 6962839Abstract: The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intrinsic characters of metal and semiconductor, so it can be the channel, connector or next-level gate of transistor. Furthermore, the transistor has the structure of exchangeable source and drain, and can be defined the specificity by outside wiring.Type: GrantFiled: July 29, 2004Date of Patent: November 8, 2005Assignee: Industrial Technology Research InstituteInventors: Jeng-Hua Wei, Hsin-Hui Chen, Ming-Jiunn Lai, Hung-Hsiang Wang, Ming-Jer Kao
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Publication number: 20050233585Abstract: A metal nanoline process and applications on growth of aligned nanostructures thereof. A nano-structure is provided with a substrate with at least one nanodimensional metal catalyst line disposed thereon and at least one carbon nanotube or silicon nanowire extending along an end of the metal catalyst line.Type: ApplicationFiled: October 21, 2004Publication date: October 20, 2005Inventors: Ming-Jiunn Lai, Jeng-Hua Wei, Hung-Hsiang Wang, Po-Yuan Lo, Ming-Jer Kao