Patents by Inventor Jeng-Jung Shen
Jeng-Jung Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8881084Abstract: A method for generating a layout for a semiconductor device is disclosed. The method includes: receiving a first layout. A portion of the first layout is defined as a first FinFET region. The first FinFET region has first and second sides that each extend approximately in a first direction. The method includes performing a first design rule check (DRC) simulation. The method includes obtaining a first DRC simulation result. The method includes defining a second FinFET region by moving the first side in a second direction perpendicular to the first direction. The method includes performing a second DRC simulation. The method includes obtaining a second DRC simulation result. The method includes selecting one of the first and second FinFET regions based on the first and second DRC simulation results. The method includes generating a second layout using the selected FinFET region.Type: GrantFiled: May 14, 2010Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Jung Shen, Shao-Ming Yu, Chih-Sheng Chang
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Patent number: 8653630Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.Type: GrantFiled: March 12, 2013Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhon Jhy Liaw, Jeng-Jung Shen
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Patent number: 8621398Abstract: A method for generating a layout for a FinFET device is disclosed. The method includes receiving an initial layout containing an active region that has an edge extending in a first direction. The method includes designating a portion of the layout as a first region. The first region contains the active region. The method includes designating an elongate portion of the first region as a second region that extends in the first direction. The method includes designating a different elongate portion of the first region as a third region that extends in the first direction and that is adjacent to the second region in a second direction perpendicular to the first direction. The method includes enlarging the active region if the edge of the active region falls inside the third region, and shrinking the active region if the edge of the active region falls outside the third region.Type: GrantFiled: May 14, 2010Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Jung Shen, Shao-Ming Yu, Chih-Sheng Chang
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Publication number: 20130200395Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.Type: ApplicationFiled: March 12, 2013Publication date: August 8, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhon Jhy Liaw, Jeng-Jung Shen
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Patent number: 8399931Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.Type: GrantFiled: June 30, 2010Date of Patent: March 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhon Jhy Liaw, Jeng-Jung Shen
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Publication number: 20120001197Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhon Jhy Liaw, Jeng-Jung Shen
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Publication number: 20110283245Abstract: A method for generating a layout for a FinFET device is disclosed. The method includes receiving an initial layout containing an active region that has an edge extending in a first direction. The method includes designating a portion of the layout as a first region. The first region contains the active region. The method includes designating an elongate portion of the first region as a second region that extends in the first direction. The method includes designating a different elongate portion of the first region as a third region that extends in the first direction and that is adjacent to the second region in a second direction perpendicular to the first direction. The method includes enlarging the active region if the edge of the active region falls inside the third region, and shrinking the active region if the edge of the active region falls outside the third region.Type: ApplicationFiled: May 14, 2010Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng-Jung Shen, Shao-Ming Yu, Chih-Sheng Chang
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Publication number: 20110282478Abstract: A method for generating a layout for a semiconductor device is disclosed. The method includes: receiving a first layout. A portion of the first layout is defined as a first FinFET region. The first FinFET region has first and second sides that each extend approximately in a first direction. The method includes performing a first design rule check (DRC) simulation. The method includes obtaining a first DRC simulation result. The method includes defining a second FinFET region by moving the first side in a second direction perpendicular to the first direction. The method includes performing a second DRC simulation. The method includes obtaining a second DRC simulation result. The method includes selecting one of the first and second FinFET regions based on the first and second DRC simulation results. The method includes generating a second layout using the selected FinFET region.Type: ApplicationFiled: May 14, 2010Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng-Jung Shen, Shao-Ming Yu, Chih-Sheng Chang
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Patent number: RE47409Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.Type: GrantFiled: February 11, 2016Date of Patent: May 28, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhon Jhy Liaw, Jeng-Jung Shen
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Patent number: RE49203Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions foamed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.Type: GrantFiled: May 24, 2019Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhon Jhy Liaw, Jeng-Jung Shen