Patents by Inventor Jeng-Kuo Jeng

Jeng-Kuo Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6140826
    Abstract: The present invention is concerned with a method and apparatus for performing a failure analysis on an integrated circuit chip package by mounting the package in a printed circuit board that is equipped with a recess (or an aperture) adapted for receiving the package and then making an electrical connection between the pin leads on the package and the terminals on the board such that when a backside surface layer of the package is later removed to expose the active circuit in the chip, the electrical connection between the chip and the board is substantially maintained so that a bias voltage can be fed into the chip to perform the failure analysis.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: October 31, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Jeng-Kuo Jeng
  • Patent number: 6020748
    Abstract: The present invention is concerned with a method and apparatus for performing a failure analysis on an integrated circuit chip package by mounting the package in a printed circuit board that is equipped with a recess (or an aperture) adapted for receiving the package and then making an electrical connection between the pin leads on the package and the terminals on the board such that when a backside surface layer of the package is later removed to expose the active circuit in the chip, the electrical connection between the chip and the board is substantially maintained so that a bias voltage can be fed into the chip to perform the failure analysis.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: February 1, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Jeng-Kuo Jeng