Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.

Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.

Abstract: A method for electron-beam writing to a medium includes positioning the medium within an e-beam writing machine so that the medium is supported by a stage and is exposed to an e-beam source. The method also includes writing a pattern to the medium using a plurality of independently-controllable beams of the e-beam source, in which the pattern comprises a plurality of parallel strips. Each of the parallel strips is written using multiple ones of the independently-controllable beams.

Abstract: Immersion lithography system and method using direction-controlling fluid inlets are described. According to one embodiment of the present disclosure, an immersion lithography apparatus includes a lens assembly having an imaging lens disposed therein and a wafer stage configured to retain a wafer beneath the lens assembly. The apparatus also includes a plurality of direction-controlling fluid inlets disposed adjacent to the lens assembly, each direction-controlling fluid inlet in the plurality of direction-controlling fluid inlets being configured to direct a flow of fluid beneath the lens assembly and being independently controllable with respect to the other fluid inlets in the plurality of direction-controlling fluid inlets.

Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.

Abstract: A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask.

Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.

Abstract: A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended.

Abstract: An optical engine assembly includes a bench, an optoelectronic device, a fixed member and a plurality of fibers. The bench has a bearing surface and an extended sidewall with a predetermined height from the bearing surface. The sidewall has an upper surface parallel to the bearing surface. The optoelectronic device is disposed on the center of the upper surface and includes a plurality of active areas. The fixed member is disposed on the bearing surface and has a plurality of through holes and two pin holes. The fibers respectively pass through the through holes and a 45-degree beveled surface is formed at the front end of each fiber. The 45-degree beveled surfaces are aligned with the active areas, respectively.

Abstract: An apparatus for immersion lithography that includes an imaging lens which has a front surface, a fluid-containing wafer stage for supporting a wafer that has a top surface to be exposed positioned spaced-apart and juxtaposed to the front surface of the imaging lens, and a fluid that has a refractive index between about 1.0 and about 2.0 filling a gap formed in-between the front surface of the imaging lens and the top surface of the wafer. A method for immersion lithography can be carried out by flowing a fluid through a gap formed in-between the front surface of an imaging lens and a top surface of a wafer. The flow rate and temperature of the fluid can be controlled while particulate contaminants are filtered out by a filtering device.

Abstract: A method and system for simultaneously processing multiple substrates through an imaging beam process is provided. The system includes a plurality of direct write substrate exposure modules configured to receive a writing instruction from a data processing unit. The system and method of the invention utilizes multiple exposure modules receiving writing instructions from a single common data processing unit.

Abstract: An apparatus for immersion lithography that includes an imaging lens which has a front surface, a fluid-containing wafer stage for supporting a wafer that has a top surface to be exposed positioned spaced-apart and juxtaposed to the front surface of the imaging lens, and a fluid that has a refractive index between about 1.0 and about 2.0 filling a gap formed in-between the front surface of the imaging lens and the top surface of the wafer. A method for immersion lithography can be carried out by flowing a fluid through a gap formed in-between the front surface of an imaging lens and a top surface of a wafer. The flow rate and temperature of the fluid can be controlled while particulate contaminants are filtered out by a filtering device.

Abstract: A resist material and methods using the resist material are disclosed herein. An exemplary method includes forming a resist layer over a substrate, wherein the resist layer includes a polymer, a photoacid generator, an electron acceptor, and a photodegradable base; performing an exposure process that exposes portions of the resist layer with radiation, wherein the photodegradable base is depleted in the exposed portions of the resist layer during the exposure process; and performing an developing process on the resist layer.

Abstract: A backlight module provided includes a light source, a first light-guided plate, and a second light-guided plate stacked on the first light-guided plate. The first light-guided plate includes a plate body and an extension disposed on an edge of the plate body and extending towards the second light-guided plate aside a lateral side of the second light-guided plate. The plate body and the extension form a seamless light incident surface. The extension has a reflection surface. The reflection surface connects the light incident surface or the surface of the plate body. The light source is disposed at a light incident surface of the first light-guided plate for projecting light into the light-guided plate.

Abstract: A portable electronic device includes a main body and a heat dissipation module with a tiltedly installed centrifugal fan inside thereof. The main body includes an upper housing wall and a lower housing wall. The heat dissipation module includes a centrifugal fan, a heat dissipation fin array and a heat pipe. The centrifugal fan includes an impeller, a radial air outlet, an upper axial air inlet and a lower axial air inlet, wherein the centrifugal fan has a first side that is in contact with the upper housing wall and an opposite second side that is in contact with the lower housing wall. The heat dissipation fin array is located at the radial air outlet of the centrifugal fan. The heat pipe has a first end connected with the heat dissipation fin array and a second opposite end connected with a heat source.

Abstract: A heat dissipation module includes a centrifugal fan and a heat dissipation fin array. The centrifugal fan includes at least one axial air inlet and a radial air outlet, wherein the radial air outlet is defined between a first sidewall and an opposite second sidewall with a tongue potion. The heat dissipation fin array is located at the radial air outlet of the centrifugal fan. The heat dissipation fin array and the radial air outlet substantially share an equal length L. The heat dissipation fin array has a middle wind stop section which is closer to the second sidewall than the first sidewall. The wind stop section has a length ranging from about 0.1 L to about 0.42 L.

Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.