Patents by Inventor Jeng Lin

Jeng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH-VOLUME MANUFACTURING MASSIVE E-BEAM MASKLESS LITHOGRAPHY SYSTEM
    Publication number: 20100248158
    Abstract: The present disclosure provides a maskless lithography apparatus. The apparatus includes a plurality of writing chambers, each including: a wafer stage operable to secure a wafer to be written and a multi-beam module operable to provide multiple radiation beams for writing the wafer; an interface operable to transfer wafers between each of the writing chambers and a track unit for processing an imaging layer to the wafers; and a data path operable to provide a set of circuit pattern data to each of the multiple radiation beams in each of the writing chambers.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Horng Chen, Shy-Jay Lin, Burn Jeng Lin
  • Resist collapse prevention using immersed hardening
    Patent number: 7767984
    Abstract: A method, tool, and machine for hardening a photoresist image while the photoresist image is immersed in a liquid.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: August 3, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Burn-Jeng Lin, Ching-Yu Chang
  • Immersion Fluid for Immersion Lithography, and Method of Performing Immersion Lithography
    Publication number: 20100177289
    Abstract: An immersion lithographic system 10 comprises an optical surface 51, an immersion fluid 60 with a pH less than 7 contacting at least a portion of the optical surface, and a semiconductor structure 80 having a topmost photoresist layer 70 wherein a portion of the photoresist is in contact with the immersion fluid. Further, a method for illuminating a semiconductor structure 80 having a topmost photoresist layer 70 comprising the steps of: introducing an immersion fluid 60 into a space between an optical surface 51 and the photoresist layer wherein the immersion fluid has a pH of less than 7, and directing light preferably with a wavelength of less than 450 nm through the immersion fluid and onto the photoresist.
    Type: Application
    Filed: March 25, 2010
    Publication date: July 15, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Burn-Jeng Lin, Chenming Hu
  • Structure For Eliminating Bright Line Of Tiled Backlight Module
    Publication number: 20100142219
    Abstract: A structure for eliminating bright lines of a tiled backlight module is provided. The structure includes a light guide plate, and a plurality of light sources. The light guide plate includes a plurality of rows of optical elements. The rows of optical elements extend in parallel. The light sources are provided at least one side of the light guide plate for projecting a light into the light guide plate and generating a regular but non-uniform light outputting performance of the light guide plate. Therefore, a brightness of areas where the optical elements are located is higher than the rest areas, so that the light guide plate achieves a regular but non-uniform light emitting performance. Accordingly, the bright lines occurred at joints between two light guide plates are enshrouded by the high brightness areas, and become hard to identify or even undistinguishable, thus “eliminated”.
    Type: Application
    Filed: October 19, 2009
    Publication date: June 10, 2010
    Inventors: Sheng-Ju Chung, Tung-Chuan Su, Yu-Jeng Lin, Wen-Yen Huang, Yi-Chieh Lu
  • Immersion fluid for immersion lithography, and method of performing immersion lithography
    Patent number: 7700267
    Abstract: An immersion lithographic system 10 comprises an optical surface 51, an immersion fluid 60 with a pH less than 7 contacting at least a portion of the optical surface, and a semiconductor structure 80 having a topmost photoresist layer 70 wherein a portion of the photoresist is in contact with the immersion fluid. Further, a method for illuminating a semiconductor structure 80 having a topmost photoresist layer 70 comprising the steps of: introducing an immersion fluid 60 into a space between an optical surface 51 and the photoresist layer wherein the immersion fluid has a pH of less than 7, and directing light preferably with a wavelength of less than 450 nm through the immersion fluid and onto the photoresist.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: April 20, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Burn-Jeng Lin, Chenming Hu
  • LIQUID CRYSTAL LENS WITH VARIABLE FOCUS
    Publication number: 20100053539
    Abstract: A liquid crystal lens with variable focus formed by a single layer or multiple layers of liquid crystal lens unit is revealed. The liquid crystal lens unit includes two glass substrates with preset thickness and arranged in parallel so as to form a middle space for accommodation of liquid crystal layer. By etching, an aluminum membrane, silver membrane or other transparent metal membranes to form surface electrode patterns that can be controlled independently. The arrangement and the refractive index of each liquid crystal layer can be tuned by adjustment of the applied voltage so as to improve image quality, increase focus switch speed, improve easiness of assembling, reduce whole thickness of the lens, and the manufacturing cost.
    Type: Application
    Filed: March 23, 2009
    Publication date: March 4, 2010
    Inventor: Jau-Jeng LIN
  • Electric variable inertia apparatus
    Patent number: 7666114
    Abstract: An electric variable inertia apparatus uses a servo drive device to drive a planetary gear mechanism to which a load assembly is attached to provide variable and wide-ranging rotational inertia. A planetary frame and a ring gear of the planetary gear mechanism act as two input ends of the electric variable inertia apparatus, and a rotated shaft of a sun gear assembly of the planetary gear mechanism acts as a load terminal. The load assembly is rotated at a controlled rotational velocity with the ring gear to generate a widely ranging rotational inertia to change a dissipating degree of an input energy from the planetary frame. The electric variable inertia apparatus can be used in different fields such as shock absorbers, stabilizers, dampers or vibrators in the automotive field, etc.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: February 23, 2010
    Assignee: National Formosa University
    Inventors: Bor-Jeng Lin, Mi-Ching Tsai, Cheng-Chi Huang, Li-Jung Tu
  • Exposure scan and step direction optimization
    Patent number: 7666576
    Abstract: A lithography process to pattern a plurality of fields on a substrate is disclosed. The process includes scanning a first field along a first direction using a radiation beam. Thereafter, the processes steps to a second field adjacent the first field and located behind the first field when the first and second fields are viewed along the first direction. The second field is then scanned along the first direction using the radiation beam.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: February 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Jye Liang, Lin-Hung Shiu, Chun-Kuang Chen, Tsai-Sheng Gau, Burn Jeng Lin
  • Level adjustment systems and adjustable pin chuck thereof
    Patent number: 7659964
    Abstract: A level adjustment system. The level adjustment system includes an adjustable pin chuck, an evacuation device, a level detection device and a length control device. The adjustable pin chuck includes a base and a variable pin to support a substrate. The base includes a recess and an evacuation channel connected thereto. The variable pin is disposed in the recess. The evacuation device is connected to the evacuation channel to evacuate the recess, such that the substrate is attached to the base and variable pin. The level detection device is disposed on the adjustable pin chuck to detect the horizontality of a target surface of the substrate. The length control device is electrically connected to the level detection device and variable pin. The length control device changes the length of the variable pin to adjust level of the target surface of the substrate according to the detected horizontality.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: February 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Burn-Jeng Lin, Tsai-Sheng Gau, Jeng-Horng Chen
  • Manufacturing method of static random access memory
    Patent number: 7638390
    Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: December 29, 2009
    Assignee: United Microelectric Corp.
    Inventors: Tzung-Han Lee, Kuang-Pi Lee, Wen-Jeng Lin, Rern-Hurng Larn
  • METHOD AND APPARATUS FOR PLANARIZING A POLYMER LAYER
    Publication number: 20090309253
    Abstract: A method for planarizing a polymer layer is provided which includes providing a substrate having the polymer layer formed thereon, providing a structure having a substantially flat surface, pressing the flat surface of the structure to a top surface of the polymer layer such that the top surface of the polymer layer substantially conforms to the flat surface of the structure, and separating the flat surface of the structure from the top surface of the polymer material layer.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 17, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Burn Jeng Lin
  • System and Method for Direct Writing to a Wafer
    Publication number: 20090268184
    Abstract: A direct-write (DW) exposure system is provided which includes a stage for holding a substrate and configured to scan the substrate along an axis during exposure, a data processing module for processing pattering data and generating instructions associated with the patterning data, and an exposure module that includes a plurality of beams that are focused onto the substrate such that the beams cover a width that is larger than a width of a field size and a beam controller that controls the plurality of beams in accordance with the instructions as the substrate is scanned along the axis. The widths are in a direction different from the axis.
    Type: Application
    Filed: September 3, 2008
    Publication date: October 29, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Burn Jeng Lin, Jeng-Horng Chen, Shy-Jay Lin, Tsai-Sheng Gau
  • Flash storage system with data storage security
    Patent number: 7596655
    Abstract: A flash storage comprises a flash memory, including a plurality of physical memory blocks, each of physical memory blocks comprising a plurality of memory segments, and a plurality of physical sectors, and each of physical sectors being further provided therein with at least a user data column and a logical address pointer column. When physical data is written into the user data column, writing logical address pointer data into the logical address pointer column of the same physical sector may be performed together by the control of a micro-controller. Furthermore, the logical address pointer data in the same memory segment are arranged to be a backup memory segment address mapping table and then stored in one physical memory block. The backup memory segment address mapping table may be loaded directly and stored into a registered memory by the micro-controller when the system boots.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: September 29, 2009
    Assignee: Prolific Technology Inc.
    Inventors: Yu-Hsien Wang, Chanson Lin, Tung-Hsien Wu, Chien-Chang Su, Gow-Jeng Lin, Ching-Chung Hsu, Kuang-Yuan Chen
  • Air baffle and calculation method of deformational stress thereof
    Publication number: 20090233537
    Abstract: An air baffle has elasticity and is disposed in an electronic device. The air baffle may be elastically deformed under a pressure exerted by an article. The air baffle includes a fixed section and at least one deformable section extending from a lateral side of the fixed section. The deformable section is arc-shaped and has a second-order deformation. A deformational stress of the deformable section is calculated using ? = FR ? ( sin ? ? ? ) ? t 2 ? I , and an allowable radius of curvature of the deformable section is determined, so as to keeping the deformational stress of the deformable section not exceeding a material yield stress of the air baffle.
    Type: Application
    Filed: May 2, 2008
    Publication date: September 17, 2009
    Applicant: Inventec Corporation
    Inventors: Cheng-Sen Kao, Wen-Lan Yang, Ren-Jeng Lin
  • Seal Ring Arrangements for Immersion Lithography Systems
    Publication number: 20090180087
    Abstract: Various seal ring arrangements for an immersion lithography system are disclosed. With the seal ring arrangements, the immersion lithography system can provide better sealing effect for processing the wafers on a wafer chuck.
    Type: Application
    Filed: March 27, 2009
    Publication date: July 16, 2009
    Inventors: Burn Jeng Lin, Tsai-Sheng Gau, Chun-Kuang Chen, Ru-Gun Liu, Shinn Sheng Yu, Jen Chieh Shih
  • Compositions and methods for dual therapies of hair graying and balding in follicular delivery systems
    Patent number: 7524505
    Abstract: The present invention provides comprehensive compositions for treating problems associated with hair graying and balding via the incorporation of: (i) the cell growth factor of HSCF to induce the migration of melanocyte stem cells and keratinocyte stem cells and then to increase the growth of melanocytes and keratinocytes in hair follicles, (ii) a formula of amino acids and vitamins to provide the nutritional factors for hair growth and pigmentation, and (iii) minoxidil to enhance the function of HSCF on hair re-growth. The compositions comprising at least one of (i), (ii) or (iii) are administered on skin and/or scalp through liposome in the follicular delivery systems, including penetration enhancers and suitable carrier bases. The compositions packaged in liposome in the follicular delivery systems in this invention has been proven to reach the dermis from the skin surface within 15-30 min.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: April 28, 2009
    Assignee: Schweitzer Biotech Company Ltd.
    Inventors: Chai-Ching Shirley Lin, Tsun-Yung Kuo, Yun-Jeng Lin
  • Seal ring arrangements for immersion lithography systems
    Patent number: 7517639
    Abstract: Various seal ring arrangements for an immersion lithography system are disclosed. With the seal ring arrangements, the immersion lithography system can provide better sealing effect for processing the wafers on a wafer chuck.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: April 14, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Burn Jeng Lin, Tsai-Sheng Gau, Chun-Kuang Chen, Ru-Gun Liu, Shinn Sheng Yu, Jen Chieh Shih
  • Immersion lithography system with wafer sealing mechanisms
    Patent number: 7501226
    Abstract: An immersion lithography system is disclosed to comprise a fluid containing feature for providing an immersion fluid for performing immersion lithography on a wafer, and a seal ring covering a predetermined portion of a wafer edge for preventing the immersion fluid from leaking through the covered portion of the wafer edge while the fluid is used for the immersion lithography.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: March 10, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Burn Jeng Lin, Tsai-Sheng Gau, Chun-Kung Chen, Ru-Gun Liu, Shing Shen Yu, Jen Chieh Shih
  • PELLICLE STRESS RELIEF
    Publication number: 20090029268
    Abstract: The present disclosure provides a mask-pellicle system for lithography patterning. The mask-pellicle system includes a mask substrate; a predefined pattern formed on the transparent pattern; a pellicle configured approximate the transparent substrate; a pellicle frame designed to secure the pellicle; and a stress-absorbing feature configured between the pellicle frame and the mask substrate, to reduce stress of the mask substrate.
    Type: Application
    Filed: February 11, 2008
    Publication date: January 29, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Burn Jeng Lin, Hsin-Chang Lee, Ming-Jiun Yao
  • Method for forming a lithography pattern
    Patent number: 7482280
    Abstract: A method of lithography patterning includes forming a first material layer on a substrate, the first material layer being substantially free of silicon, and forming a patterned resist layer including at least one opening therein above the first material layer. A second material layer containing silicon is formed on the patterned resist layer and an opening is formed in the first material layer using the second material layer as a mask.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: January 27, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Chang, Chin-Hsiang Lin, Burn Jeng Lin