Abstract: The invention discloses a cyclic-Frequency shift orthogonal frequency division multiplex spread spectrum device, comprising: at least one communication device for performing the conversion between a series of bits and a frequency domain symbol out of a plurality of frequency combination patterns; wherein different patterns correspond to different bit values; and the device forms a cyclic frequency shift value utilizing a frequency reordering, each of the cyclic frequency shift values corresponding to a frequency combination pattern.

Abstract: A power line communication (PLC) device is provided which communicates with another PLC device via a PLC signal transmitted over a wire in a broadband. The PLC signal comprises at least one frame. The at least one frame comprises a preamble, a frame control header and a payload. The preamble comprises at least one synchronization symbols used for a PLC engine to synchronize; at least one preamble code symbols used for specifying at least one of a sub-channel and a modulation mechanism; and at least one channel estimation symbols used for the PLC engine to do channel estimation.

Abstract: A power line communication (PLC) device is provided which communicates with another PLC device via a PLC signal transmitted over a wire in a broadband. The PLC signal comprises at least one frame. The at least one frame comprises a preamble, a frame control header and a payload. The preamble comprises at least one synchronization symbols used for a PLC engine to synchronize; at least one preamble code symbols used for specifying at least one of a sub-channel and a modulation mechanism; and at least one channel estimation symbols used for the PLC engine to do channel estimation.

Abstract: The invention discloses a cyclic-Frequency shift orthogonal frequency division multiplex spread spectrum device, comprising: at least one communication device for performing the conversion between a series of bits and a frequency domain symbol out of a plurality of frequency combination patterns; wherein different patterns correspond to different bit values; and the device forms a cyclic frequency shift value utilizing a frequency reordering, each of the cyclic frequency shift values corresponding to a frequency combination pattern.

Abstract: A method of arranging a frame for power reduction, utilized in a transmitter in a communication system is disclosed. The transmitter communicates with a receiver in the communication system. The method comprises generating a preamble with a first power level in the frame; arranging a header with the first power level after the preamble in the frame, wherein the header comprises information of a second power level; arranging an additional channel estimation (ACE) symbol with the second power level after the header in the frame; and arranging a first payload with the second power level after the ACE symbol in the frame.

Abstract: One embodiment sets forth a method of scanning a frequency channel, which includes receiving a radio-frequency signal in a selected frequency channel, performing a carrier recovery process, and evaluating a control signal generated during the carrier recovery process to determine the presence of program content in the selected frequency channel.

Abstract: A method of arranging a frame for power reduction, utilized in a transmitter in a communication system is disclosed. The transmitter communicates with a receiver in the communication system. The method comprises generating a preamble with a first power level in the frame; arranging a header with the first power level after the preamble in the frame, wherein the header comprises information of a second power level; arranging an additional channel estimation (ACE) symbol with the second power level after the header in the frame; and arranging a first payload with the second power level after the ACE symbol in the frame.

Abstract: A method for estimating frequency offsets is disclosed. The method includes shifting a target signal from a first specific frequency band to a second specific frequency band to generate a pre-offset signal according to a frequency shifting direction, performing a specific filtering operation upon the pre-offset signal to generate a filtered pre-offset signal, shifting the filtered pre-offset signal from the second specific frequency band to a base band to generate a base-band (BB) signal according to the frequency shifting direction, and performing a frequency offset estimation upon the base-band signal. The target signal complies with a specific TV format. The specific TV format is an advanced television system committee (ASTC) format or a digital multimedia broadcast-terrestrial/handheld (DMB-T/H) format.

Abstract: The invention discloses a digital demodulating apparatus for timing error detection, including a numerically controlled oscillator, an equalizer unit, a decoder and a timing error detector. The numerically controlled oscillator generates a first sequence signal according to an input sequence signal and a timing error sequence signal. The equalizer unit equalizes the first sequence signal to generate an equalized sequence signal. The decoder decodes the equalized sequence signal to generate to generate an output sequence signal. The timing error detector generates the timing error sequence signal according to the first sequence signal and one of the equalized sequence signal and the output sequence signal.

Abstract: The present invention provides a method for adjusting a center frequency of a filter utilized for extracting information carried via a target channel. The method includes: detecting adjacent channel interference (ACI) for the target channel to generate a channel interference information; and adjusting the center frequency of the filter for the target channel according to the channel interference information.

Abstract: A digital demodulator adapted in a receiver and a digital demodulation method are provided. The digital demodulator includes: a phase splitter, a complex multiplier, an AFC, a limiter, a phase detector, a re-tracker, a post-multiplier and an oscillator. The phase splitter generates a complex signal from the input signal. The complex multiplier multiplies the complex signal by both first and second phase signals to generate first and second base band signals. The AFC generates a first output signal. The limiter generates a trend signal and the re-tracker generates a tuning signal from the first output signal. The phase detector multiplies the trend and second base signal and adjusts the multiplied signal based on the tuning signal. The oscillator generates the first and second phase signals according to the output of the phase detector. The post-multiplier multiplies the trend signal by the first and second base band signals for output.

Abstract: A digital receiver includes an analog front-end circuit, an automatic-gain controller, a compensation circuit, and a demodulator. The analog front-end circuit receives an input signal, adjusts an average amplitude of the input signal, and converts the adjusted input signal to generate a digital signal according to a control signal. The automatic-gain controller is coupled to the analog front-end circuit for generating the control signal feedback to the analog front-end circuit according to the digital signal. The compensation circuit is coupled to the analog front-end circuit for detecting an average amplitude of the digital signal to generate a detecting result and for determining whether to compensate the average amplitude of the digital signal to generate a compensated digital signal according to the detecting result. The demodulator is coupled to the compensation circuit for demodulating the compensated digital signal to generate an output signal.

Abstract: The invention provides carrier recovery systems and carrier recovery methods. The carrier recovery system comprises a compensation signal generator, a compensation device and a mode selector. The compensation signal generator generates a compensation signal based on a coherent demodulated signal. In a first mode, the compensate device is couple behind an equalizer; the coherent demodulated signal is generated by the compensation device which compensates the output of the equalizer with the compensation signal. In a second mode, the compensate device is coupled prior to the equalizer, compensating the output of a synchronizer with the compensation signal to generate the input of the equalizer. In the second mode, the compensation signal generator receives the output of the equalizer as the coherent demodulated signal. The mode selector switches the carrier recover system from the first mode to the second mode when an estimated frequency offset satisfies a first criterion.

Abstract: A method applied to an equalizer includes receiving an input data-stream having a training sequence component with a first number of symbols and a data component with a second number of symbols, wherein the first number plus the second number equals a third number; when a symbol number is not greater than the first number, training the training sequence component to generate a first trained coefficient set; when the symbol number is between the first number and the third number, recycling the training sequence component to generate a recycled training sequence component, and training the recycled training sequence component to generate a second trained coefficient set; storing the input data-stream to generate a delayed input data-stream when the symbol number is not greater than the third number; and applying the second trained coefficient set to the equalizer when the symbol number is greater than the third number.

Abstract: The invention discloses a digital demodulating apparatus for timing error detection, including a numerically controlled oscillator, an equalizer unit, a decoder and a timing error detector. The numerically controlled oscillator generates a first sequence signal according to an input sequence signal and a timing error sequence signal. The equalizer unit equalizes the first sequence signal to generate an equalized sequence signal. The decoder decodes the equalized sequence signal to generate to generate an output sequence signal. The timing error detector generates the timing error sequence signal according to the first sequence signal and one of the equalized sequence signal and the output sequence signal.

Abstract: A digital receiver includes an analog front-end circuit, an automatic-gain controller, a compensation circuit, and a demodulator. The analog front-end circuit receives an input signal, adjusts an average amplitude of the input signal, and converts the adjusted input signal to generate a digital signal according to a control signal. The automatic-gain controller is coupled to the analog front-end circuit for generating the control signal feedback to the analog front-end circuit according to the digital signal. The compensation circuit is coupled to the analog front-end circuit for detecting an average amplitude of the digital signal to generate a detecting result and for determining whether to compensate the average amplitude of the digital signal to generate a compensated digital signal according to the detecting result. The demodulator is coupled to the compensation circuit for demodulating the compensated digital signal to generate an output signal.

Abstract: A digital demodulator adapted in a receiver and a digital demodulation method are provided. The digital demodulator comprises: a phase splitter, a complex multiplier, an AFC, a limiter, a phase detector, a re-tracker, a post-multiplier and an oscillator. The phase splitter generates a complex signal from the input signal. The complex multiplier multiplies the complex signal by both first and second phase signals to generate first and second base band signals. The AFC generates a first output signal. The limiter generates a trend signal and the re-tracker generates a tuning signal from the first output signal. The phase detector multiplies the trend and second base signal and adjusts the multiplied signal based on the tuning signal. The oscillator generates the first and second phase signals according to the output of the phase detector. The post-multiplier multiplies the trend signal by the first and second base band signals for output.

Abstract: A method of modulation mode detection for a communication system including at least a channel transmitting signals utilizing a target modulation mode is provided. The method includes: (a) selecting a default modulation mode for the channel; (b) estimating a timing frequency offset (TFO) of the channel of the communication system for obtaining at least a TFO value and storing the TFO value; (c) comparing the TFO value with a first predetermined value to generate a comparison result; and (d) determining whether the default modulation mode is substantially identical to the target modulation mode according to the comparison result.

Abstract: The invention provides carrier recovery systems and carrier recovery methods. The carrier recovery system comprises a compensation signal generator, a compensation device and a mode selector. The compensation signal generator generates a compensation signal based on a coherent demodulated signal. In a first mode, the compensate device is couple behind an equalizer; the coherent demodulated signal is generated by the compensation device which compensates the output of the equalizer with the compensation signal. In a second mode, the compensate device is coupled prior to the equalizer, compensating the output of a synchronizer with the compensation signal to generate the input of the equalizer. In the second mode, the compensation signal generator receives the output of the equalizer as the coherent demodulated signal. The mode selector switches the carrier recover system from the first mode to the second mode when an estimated frequency offset satisfies a first criterion.

Abstract: A method applied to an equalizer includes receiving an input data-stream having a training sequence component with a first number of symbols and a data component with a second number of symbols, wherein the first number plus the second number equals a third number; when a symbol number is not greater than the first number, training the training sequence component to generate a first trained coefficient set; when the symbol number is between the first number and the third number, recycling the training sequence component to generate a recycled training sequence component, and training the recycled training sequence component to generate a second trained coefficient set; storing the input data-stream to generate a delayed input data-stream when the symbol number is not greater than the third number; and applying the second trained coefficient set to the equalizer when the symbol number is greater than the third number.