Patents by Inventor Jeng-Shin Ma

Jeng-Shin Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240282610
    Abstract: A wafer transport carrier includes various components to provide improved air sealing to reduce air leakage into the wafer transport carrier. The wafer transport carrier may include a housing having a hollow shell that contains a vacuum or an inert gas to minimize and/or prevent humidity and oxygen ingress into the wafer transport carrier, a wafer rack that is integrated into the shell of the housing to minimize and/or prevent air leakage around the wafer rack, and/or an enhanced magnet-based door latch to provide air sealing around the full perimeter of the opening of the housing. These components and/or additional components described herein may reduce and/or prevent debris, moisture, and/or other types of contamination from the semiconductor fabrication facility from entering the wafer transport carrier and causing wafer defects and/or device failures.
    Type: Application
    Filed: May 1, 2024
    Publication date: August 22, 2024
    Inventors: Jyh-Shiou HSU, Jeng-Shin MA, Cheng-Lung WU
  • Patent number: 12009242
    Abstract: A wafer transport carrier includes various components to provide improved air sealing to reduce air leakage into the wafer transport carrier. The wafer transport carrier may include a housing having a hollow shell that contains a vacuum or an inert gas to minimize and/or prevent humidity and oxygen ingress into the wafer transport carrier, a wafer rack that is integrated into the shell of the housing to minimize and/or prevent air leakage around the wafer rack, and/or an enhanced magnet-based door latch to provide air sealing around the full perimeter of the opening of the housing. These components and/or additional components described herein may reduce and/or prevent debris, moisture, and/or other types of contamination from the semiconductor fabrication facility from entering the wafer transport carrier and causing wafer defects and/or device failures.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyh-Shiou Hsu, Jeng-Shin Ma, Cheng-Lung Wu
  • Publication number: 20230060148
    Abstract: A wafer transport carrier includes various components to provide improved air sealing to reduce air leakage into the wafer transport carrier. The wafer transport carrier may include a housing having a hollow shell that contains a vacuum or an inert gas to minimize and/or prevent humidity and oxygen ingress into the wafer transport carrier, a wafer rack that is integrated into the shell of the housing to minimize and/or prevent air leakage around the wafer rack, and/or an enhanced magnet-based door latch to provide air sealing around the full perimeter of the opening of the housing. These components and/or additional components described herein may reduce and/or prevent debris, moisture, and/or other types of contamination from the semiconductor fabrication facility from entering the wafer transport carrier and causing wafer defects and/or device failures.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Jyh-Shiou HSU, Jeng-Shin MA, Cheng-Lung WU
  • Patent number: 9864270
    Abstract: A method for manufacturing a pellicle includes: providing a supporting substrate; forming an oxide layer over the supporting substrate; forming a metal layer over the oxide layer; forming a graphene layer over the metal layer; and removing at least a portion of the supporting substrate and the oxide layer. An associated method includes: providing a supporting substrate; forming a first silicon carbide (SiC) layer or a diamond layer over the supporting substrate; forming a graphene layer over the SiC layer or the diamond layer; and removing at least a portion of the supporting substrate and the first silicon carbide (SiC) layer or the diamond layer; wherein the pellicle is at least partially transparent to extreme ultraviolet (EUV) radiation. An associated pellicle is also disclosed.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jeng-Shin Ma, Tsiao-Chen Wu, Chi-Ming Yang, Chyi Shyuan Chern, Chih-Cheng Lin, Yun-Yue Lin
  • Publication number: 20170205705
    Abstract: A method for manufacturing a pellicle includes: providing a supporting substrate; forming an oxide layer over the supporting substrate; forming a metal layer over the oxide layer; forming a graphene layer over the metal layer; and removing at least a portion of the supporting substrate and the oxide layer. An associated method includes: providing a supporting substrate; forming a first silicon carbide (SiC) layer or a diamond layer over the supporting substrate; forming a graphene layer over the SiC layer or the diamond layer; and removing at least a portion of the supporting substrate and the first silicon carbide (SiC) layer or the diamond layer; wherein the pellicle is at least partially transparent to extreme ultraviolet (EUV) radiation. An associated pellicle is also disclosed.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Jeng-Shin Ma, Tsiao-Chen Wu, Chi-Ming Yang, Chyi Shyuan Chern, Chih-Cheng Lin, Yun-Yue Lin