Patents by Inventor Jeng-Shiou Chen
Jeng-Shiou Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961761Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.Type: GrantFiled: March 15, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen
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Patent number: 11682580Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.Type: GrantFiled: August 9, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
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Publication number: 20210366766Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
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Patent number: 11088021Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.Type: GrantFiled: May 26, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
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Publication number: 20210202306Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Inventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen
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Patent number: 11043453Abstract: Methods are disclosed herein for forming conductive patterns having small pitches. An exemplary method includes forming a metal line in a first dielectric layer. The metal line has a first dimension along a first direction and a second dimension along a second direction that is different than the first direction. The method includes forming a patterned mask layer having an opening that exposes a portion of the metal line along an entirety of the second dimension and etching the portion of the metal line exposed by the opening of the patterned mask layer until reaching the first dielectric layer. The metal line is thus separated into a first metal feature and a second metal feature. After removing the patterned mask layer, a barrier layer is deposited over exposed surfaces of the first metal feature and the second metal feature and a second dielectric layer is deposited over the barrier layer.Type: GrantFiled: December 18, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yuan Ting, Chung-Wen Wu, Jeng-Shiou Chen, Jang-Shiang Tsai, Jyu-Horng Shieh
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Patent number: 10985054Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: GrantFiled: July 13, 2020Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Patent number: 10950495Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.Type: GrantFiled: August 3, 2018Date of Patent: March 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen
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Publication number: 20200343128Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Publication number: 20200286779Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
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Patent number: 10714383Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: GrantFiled: May 13, 2019Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Patent number: 10679895Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.Type: GrantFiled: October 29, 2018Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
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Publication number: 20200126913Abstract: Methods are disclosed herein for forming conductive patterns having small pitches. An exemplary method includes forming a metal line in a first dielectric layer. The metal line has a first dimension along a first direction and a second dimension along a second direction that is different than the first direction. The method includes forming a patterned mask layer having an opening that exposes a portion of the metal line along an entirety of the second dimension and etching the portion of the metal line exposed by the opening of the patterned mask layer until reaching the first dielectric layer. The metal line is thus separated into a first metal feature and a second metal feature. After removing the patterned mask layer, a barrier layer is deposited over exposed surfaces of the first metal feature and the second metal feature and a second dielectric layer is deposited over the barrier layer.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Chih-Yuan Ting, Chung-Wen Wu, Jeng-Shiou Chen, Jang-Shiang Tsai, Jyu-Horng Shieh
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Patent number: 10515895Abstract: A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.Type: GrantFiled: November 21, 2016Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-yuan Ting, Chung-Wen Wu, Jeng-Shiou Chen, Jang-Shiang Tsai, Jyu-Horng Shieh
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Publication number: 20190326156Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: ApplicationFiled: May 13, 2019Publication date: October 24, 2019Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Patent number: 10290538Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: GrantFiled: February 12, 2018Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Publication number: 20190067090Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.Type: ApplicationFiled: October 29, 2018Publication date: February 28, 2019Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
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Publication number: 20180342418Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.Type: ApplicationFiled: August 3, 2018Publication date: November 29, 2018Inventors: Chih-Yuan TING, Ya-Lien LEE, Chung-Wen WU, Jeng-Shiou CHEN
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Patent number: 10115630Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.Type: GrantFiled: August 8, 2016Date of Patent: October 30, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
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Patent number: 10043706Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.Type: GrantFiled: January 18, 2013Date of Patent: August 7, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen