Patents by Inventor Jeng-Shiun Ho
Jeng-Shiun Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9748107Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: GrantFiled: October 23, 2015Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Chun Lo, Min-Hung Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai, Cheng-Cheng Kuo, Hua-Tai Lin, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 9437485Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: GrantFiled: April 4, 2014Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Cheng Kuo, Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Publication number: 20160042964Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Chun LO, Min-Hung CHENG, Hsiao-Wei SU, Jeng-Shiun HO, Ching-Che TSAI, Cheng-Cheng KUO, Hua-Tai LIN, Chia-Chu LIU, Kuei-Shun CHEN
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Patent number: 9184101Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: GrantFiled: March 11, 2013Date of Patent: November 10, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Chun Lo, Min-Hung Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai, Cheng-Cheng Kuo, Hua-Tai Lin, Chia-Chu Liu, Kuei-Shun Chen
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Publication number: 20140256144Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Chun LO, Min-Hung CHENG, Hsiao-Wei SU, Jeng-Shiun HO, Ching-Che TSAI, Cheng-Cheng KUO, Hua-Tai LIN, Chia-Chu LIU, Kuei-Shun CHEN
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Publication number: 20140208283Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: ApplicationFiled: April 4, 2014Publication date: July 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Cheng Kuo, Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Patent number: 8765329Abstract: The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.Type: GrantFiled: November 5, 2010Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiun Ho, Luke Lo, Ting-Chun Liu, Min-Hung Cheng, Jing-Wei Shih, Wen-Han Chu, Cheng-Cheng Kuo, Hua-Tai Lin, Tsai-Sheng Gau, Ru-Gun Liu, Yu-Hsiang Lin, Shang-Yu Huang
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Patent number: 8692351Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: GrantFiled: April 2, 2010Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Cheng Kuo, Luke Lo, Minghsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Patent number: 8381153Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.Type: GrantFiled: September 17, 2010Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J. H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
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Publication number: 20120115073Abstract: The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.Type: ApplicationFiled: November 5, 2010Publication date: May 10, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng-Shiun Ho, Luke Lo, Ting-Chun Liu, Min-Hung Cheng, Jing-Wei Shih, Wen-Han Chu, Cheng-Cheng Kuo, Hua-Tai Lin, Tsai-Sheng Gau, Ru-Gun Liu, Yu-Hsiang Lin, Shang-Yu Huang
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Publication number: 20120072874Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J.H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
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Publication number: 20110241207Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: ApplicationFiled: April 2, 2010Publication date: October 6, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng Cheng Kuo, Luke Lo, Minghsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Publication number: 20090258302Abstract: A photomask including a main feature, corresponding to an integrated circuit feature, and a sub-resolution assist feature (SRAF) is provided. A first imaginary line tangential with a first edge of the main feature and a second imaginary line tangential with the second edge of the main feature define an area adjacent the main feature. A center point of the SRAF lies within this area. The SRAF may be a symmetrical feature. In an embodiment, the center point of the SRAF lies on an imaginary line extending at approximately 45-degree angle from a corner of a main feature.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng-Shiun Ho, Jun-Hua Chen, Luke Lo, Louis Lin, Bing-Syun Yeh, Cheng-Cheng Kuo, Hua-Tai Lin