Patents by Inventor Jeng-Shu Liu

Jeng-Shu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070121263
    Abstract: A timing controller chip including a first resistor, a second resistor, a first electrostatic discharge (ESD) protection circuit, a second ESD protection circuit, and an operational amplifier is provided. Wherein, the first and the second resistors are electrically coupled to a first and a second low voltage differential signal (LVDS) input pins of the timing controller chip, respectively. The first and the second ESD protection circuits are electrically coupled to the first and the second resistors, respectively. Moreover, the operational amplifier has a non-inverting input terminal electrically coupled to the first resistor and the first ESD protection circuit, and an inverting input terminal is electrically coupled to the second resistor and the second ESD protection circuit.
    Type: Application
    Filed: January 20, 2006
    Publication date: May 31, 2007
    Inventors: Jeng-Shu Liu, Jen-Ta Yang, Chien-Cheng Tu
  • Publication number: 20050286187
    Abstract: ESD preventing-able level shifter, for receiving a first signal and outputting a second signal is provided. The level shifter comprises an inverter, a voltage converter, a first ESD clamp circuit and a second ESD clamp circuit. The inverter receives the first signal and outputs a first reverse signal. The voltage converter having a first input terminal for receiving the first reverse signal, a second input terminal for receiving the first signal and an output terminal for outputting the second signal. A first and second terminal of the first ESD clamp circuit is coupled to the first input terminal of the voltage converter and a second ground voltage, respectively. A first and a second terminal of the second ESD clamp circuit is coupled to the second input terminal of the voltage converter and the second ground voltage, respectively.
    Type: Application
    Filed: September 25, 2004
    Publication date: December 29, 2005
    Inventors: Jeng-Shu Liu, Shyy-Cheng Liao, Chyh-Yih Chang
  • Patent number: 6039857
    Abstract: The present invention relates to a method for forming a polyoxide film on a doped polysilicon layer, which is suitable for use as an inter-polysilicon polyoxide film between a doped polysilicon floating gate and a doped polysilicon control gate. The method includes conducting an electrolytic reaction at a room, temperature such that a polyoxide layer is formed on a doped polysilicon layer acting as an anode. The polyoxide layer is preferably further subjected with a rapid thermal processing to improve its electrical characteristics.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: March 21, 2000
    Inventors: Ching-Fa Yeh, Jeng-Shu Liu