Patents by Inventor JENG-SIAN WU

JENG-SIAN WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395465
    Abstract: A semiconductor package with improved solderability at sidewall includes a chip, a molding compound encapsulating the chip, and multiple leads distributed at sidewalls of the semiconductor package. The leads are formed as a conductive layer that is electrically connected to bonding pads of the chip. Each of the leads has a stepped surface exposed from the molding compound, wherein the stepped surface is shaped by two sequentially overlapped photoresist layers. The stepped surface of each lead allows to accommodate more solder to enhance the reliability of a solder joint between the semiconductor and a printed circuit board. Therefore, the solder joints of the semiconductor package are easily inspected by automatic optical inspection (AOI) equipment.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: CHUNG-HSIUNG HO, WEI-MING HUNG, CHI-HSUEH LI, CHIEN-CHUN WANG, JENG-SIAN WU