Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.

Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

Abstract: A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.

Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

Abstract: A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

Abstract: A memory device includes a semiconductor substrate having spaced apart source and drain regions, with a channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the channel region by insulation material having a first thickness, wherein the floating gate has a sloping upper surface that terminates in a sharp edge, a word line gate of polysilicon disposed over and insulated from a second portion of the channel region by insulation material having a second thickness, and an erase gate of polysilicon disposed over and insulated from the source region by insulation material having a third thickness, wherein the erase gate includes a notch that wraps around and is insulated from the sharp edge of the floating gate. The third thickness is greater than the first thickness, and the first thickness is greater than the second thickness.

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

Abstract: A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

Abstract: A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

Abstract: A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.

Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.