Patents by Inventor Jeng-Ya David Yeh

Jeng-Ya David Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10164065
    Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-Ya David Yeh
  • Publication number: 20180350927
    Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
  • Publication number: 20180350956
    Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.
    Type: Application
    Filed: June 22, 2017
    Publication date: December 6, 2018
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Chih-Yang YEH, Jeng-Ya David YEH
  • Publication number: 20180342595
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.
    Type: Application
    Filed: June 21, 2017
    Publication date: November 29, 2018
    Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Shu-Hui WANG, Chih-Yang YEH, Jeng-Ya David YEH
  • Publication number: 20180337092
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Hui-Chi CHEN, Hsiang-Ku SHEN, Jeng-Ya David YEH
  • Patent number: 10134872
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-De Chiou, Janet Chen, Jeng-Ya David Yeh
  • Patent number: 10128156
    Abstract: A FinFET device and a method for fabricating the same are provided. In the method for fabricating the FinFET device, at first, a semiconductor substrate having fin structures is provided. Then, a dielectric layer and a dummy gate structure are sequentially formed on the semiconductor substrate. The dummy gate structure includes two dummy gate stacks, a gate isolation structure formed between and adjoining the dummy gate stacks, and two spacers sandwiching the dummy gate stacks and the gate isolation structure. Then, the dummy gate stacks are removed to expose portions of the dielectric layer and to expose sidewalls of portions of the spacers. Thereafter, an oxidizing treatment is conducted on the exposed portions of the dielectric layer and the portions of the spacers to increase quality of the dielectric layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Wen-Li Chiu, Chun-Sheng Liang, Jeng-Ya David Yeh
  • Patent number: 10096599
    Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez
  • Publication number: 20180269213
    Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.
    Type: Application
    Filed: May 22, 2018
    Publication date: September 20, 2018
    Inventors: Jui-Yao LAI, Sai-Hooi YEONG, Yen-Ming CHEN, Ying-Yan CHEN, Jeng-Ya David YEH
  • Patent number: 10056407
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer. The semiconductor device further includes a first protective layer formed over the first cap insulating layer and at least one of the first sidewall spacers. The first protective layer includes at least one selected from the group consisting of AlON, AlN and amorphous silicon.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsiang-Ku Shen, Yu-Lien Huang, Wilson Huang, Janet Chen, Jeng-Ya David Yeh
  • Patent number: 9997522
    Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Yao Lai, Sai-Hooi Yeong, Yen-Ming Chen, Ying-Yan Chen, Jeng-Ya David Yeh
  • Publication number: 20180138176
    Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Hsiang-Ku SHEN, Chih Wei LU, Janet CHEN, Jeng-Ya David YEH
  • Patent number: 9947594
    Abstract: A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack includes N-work function metal present on the first semiconductor channel. The second gate stack includes N-work function metal present on the second semiconductor channel. The N-work function metal in the first gate stack and the second gate stack are substantially different. The difference includes at least one of N-work function metal type and N-work function metal amount.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yang Yeh, Shun-Jang Liao, Shu-Hui Wang, Chun-Sheng Liang, Kuo-Hua Pan, Jeng-Ya David Yeh
  • Publication number: 20180082908
    Abstract: A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack includes N-work function metal present on the first semiconductor channel. The second gate stack includes N-work function metal present on the second semiconductor channel. The N-work function metal in the first gate stack and the second gate stack are substantially different. The difference includes at least one of N-work function metal type and N-work function metal amount.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Chih-Yang Yeh, Shun-Jang Liao, Shu-Hui Wang, Chun-Sheng Liang, Kuo-Hua Pan, Jeng-Ya David Yeh
  • Patent number: 9893062
    Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Chih Wei Lu, Janet Chen, Jeng-Ya David Yeh
  • Publication number: 20170365674
    Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.
    Type: Application
    Filed: December 1, 2016
    Publication date: December 21, 2017
    Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
  • Publication number: 20170317076
    Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.
    Type: Application
    Filed: April 28, 2016
    Publication date: November 2, 2017
    Inventors: Hsiang-Ku SHEN, Chih Wei LU, Janet CHEN, Jeng-Ya David YEH
  • Publication number: 20170256568
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer. The semiconductor device further includes a first protective layer formed over the first cap insulating layer and at least one of the first sidewall spacers. The first protective layer includes at least one selected from the group consisting of AlON, AlN and amorphous silicon.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 7, 2017
    Inventors: Hsiang-Ku SHEN, Yu-Lien HUANG, Wilson HUANG, Janet CHEN, Jeng-Ya David YEH
  • Publication number: 20170186743
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 29, 2017
    Inventors: Yao-De CHIOU, Janet CHEN, Jeng-Ya David YEH
  • Publication number: 20170186849
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
    Type: Application
    Filed: June 13, 2016
    Publication date: June 29, 2017
    Inventors: Hui-Chi CHEN, Hsiang-ku SHEN, Jeng-Ya David YEH