Abstract: An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

Abstract: A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.

Abstract: A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.

Abstract: An emitter follower circuit with feed forward compensation includes an emitter follower having an emitter follower input and an emitter follower output. An auxiliary emitter follower has an auxiliary emitter follower input and an auxiliary emitter follower output. The emitter follower input is coupled to the auxiliary emitter follower input and the emitter follower output is capacitively coupled to the auxiliary emitter follower output. In this manner, ringing of the emitter follower circuit with feed forward compensation is reduced by the capacitive coupling of the auxiliary emitter follower output to the emitter follower output.

Abstract: A system and method are disclosed for reading data from a magnetic disk. The method includes generating a preamplified data signal by reading the magnetic state of the disk using a magnetoresistive head. The preamplified data signal is capacitively coupled to a variable gain read channel amplifier. The variable gain read channel amplifier has an input, an output, and a programmable gain. The input of the variable gain read channel amplifier has a variable gain read channel amplifier input resistance. The occurrence of a thermal asperity event is detected and an adjustment is made to the variable gain read channel amplifier input resistance to compensate for the thermal asperity event. An adjustment to the programmable gain of the variable gain read channel amplifier is made to compensate for the adjustment to the variable gain read channel amplifier input resistance.

Abstract: Analog-to-digital converter (ADC) output bits are partitioned in a way that simplifies the phase error calculations. The circuit architecture embeds the implementation of the phase error calculations in the analog-to digital-converter (ADC) to simplify the overall circuit implementation. Simplification of the phase error calculations allows a reduction in the complexity of the circuits needed to implement the phase-locked-loop (PLL) for recovering the sampling clock.

Abstract: Analog-to-digital (ADC) output bits are partitioned in a way that simplifies the gain error calculations. Simplification of the gain error calculations allows a reduction in the complexity of the circuits needed to implement automatic gain control (AGC).

Abstract: A timing acquisition circuit using a phase locked loop with programmable damping for either Type A or Type B phase detectors is described. In the damping scheme for a Type A phase detector, a resistance (R1) is simulated by adding an equivalent voltage Veff to the capacitor voltage. The equivalent voltage Veff is generated internally, so that programmable damping is made possible. In Type B phase detectors, a variable gain amplifier is used to control the effective resistance (R1) of the loop filter.

Abstract: The present invention provides a method and an apparatus for controlling initial transients in a frequency synthesizer by controlling the start-up sequence of the device. The start-up sequence comprises several steps. The voltage controlled oscillator(s) (VCO) is reset so that the VCO(s) are in a known state during start-up. The charge pump and phase detector of phase-locked loop (PLL) are disabled. New data values are loaded into counter(s)/register(s) that control the frequency of the VCO(s). Also, a data value is provided to a digital-to-analog converter (DAC) to set the data rate for the PLL. A fixed amount of time is provided as a delay for the DAC to settle (i.e., 1.6 .mu.s). Divide-by-M and divide-by-N counters are then enabled. Also, the phase detector of the phase-locked loop (PLL) is enabled. The VCO is then restarted.

Abstract: A one-shot control mechanism for ensuring close tracking of one-shot period to VCO period. The one-shot control mechanism provides immunity to data jitter and other spurious phenomena as well as stable and accurate tracking of one-shot period even when the VCO frequency varies from the center frequency of the VCO. The present invention includes a data capture PLL circuit and a frequency reference PLL circuit. The frequency reference PLL circuit provides a control signal to one or more one-shots to control their output pulse duration. Since the frequency reference PLL circuit operates at the expected frequency of data input, a relatively constant relationship may be maintained between the output pulse duration of the one-shots and the period of the VCO output.