Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: A method includes forming a metal-insulator-semiconductor (MIS) structure, in which the MIS structure includes a semiconductor layer, an insulating layer over the semiconductor layer, and a metal electrode layer over the insulating layer; performing a soft breakdown process to the MIS structure to form a local breakdown portion in the insulating layer; performing a first write operation by supplying a first voltage pulse; performing a first read operation by supplying a second voltage pulse and detecting a first read current flowing through the MIS structure; performing a second write operation by supplying a third voltage pulse, in which the first voltage pulse has a higher voltage level than the third voltage pulse; and performing a second read operation by supplying a fourth voltage pulse and detecting a second read current flowing through the MIS structure, in which the first read current is different from the second read current.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: A semiconductor device includes a substrate, a sensing device, and a transistor. The sensing device includes a dielectric layer, a sensing pad, a first sensing electrode, and a second sensing electrode. The dielectric layer is over the substrate. The sensing pad is over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode are over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode surround the sensing pad, and a distance between the first sensing electrode and the second sensing electrode is greater than a distance between the sensing pad and the first sensing electrode. The transistor is over the substrate. A gate of the transistor is connected to the sensing pad.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: A device includes a substrate, a first electrode and a second electrode. The first electrode is disposed on the substrate, and configured to receive an input signal. The second electrode is disposed on the substrate, and configured to output an output signal based on the input signal. When the input signal is configured to oscillate within a first range between a first voltage value and a second voltage value with a first frequency, the output signal is an inverted version of the input signal, and has the first frequency. When the input signal is configured to oscillate within a second range including the first voltage value without the second voltage value with the first frequency, the output signal has a second frequency which is approximately twice of the first frequency.

Abstract: A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.

Abstract: An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.

Abstract: A memory device includes a semiconductor substrate and a memory cell at a memory region of the semiconductor substrate. A memory cell includes a memory portion of the semiconductor substrate, a tunneling layer, a storage layer, a first electrode, and a second electrode. The tunneling layer is over the memory portion of the semiconductor substrate. The storage layer is over and in contact with the tunneling layer. The first electrode is over the storage layer. The second electrode is over and in contact with the tunneling layer but is spaced apart from the storage layer.

Abstract: A memory device includes a transistor, a memory cell, and an interconnect layer. The transistor includes a bottom source/drain portion, a channel portion, and a top source/drain portion stacked from bottom to top and a gate structure surrounding the channel portion. The memory cell includes a nanowire bottom electrode, a first dielectric layer, a second dielectric layer, and a top electrode. The first dielectric layer laterally surrounds the nanowire bottom electrode. The second dielectric layer is over the nanowire bottom electrode and the first dielectric layer. The second dielectric layer is in contact with a top surface of the nanowire bottom electrode and a sidewall of the first dielectric layer. The top electrode covers the second dielectric layer. The interconnect layer is over the transistor and the memory cell to interconnect the transistor and the memory cell.

Abstract: A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other.

Abstract: A device includes a substrate, a dielectric structure, a gate electrode, and a drain electrode. The dielectric structure is over the substrate. The dielectric structure includes a first portion, a second portion, and a third portion. The first portion has a first equivalent oxide thickness. The second portion is spaced apart from the first portion and has a second equivalent oxide thickness. The third portion laterally surrounds the first and second portions and has a third equivalent oxide thickness greater than the first equivalent oxide thickness of the first portion. The gate electrode is over the dielectric structure and in contact with the first and third portions of the dielectric structure. The drain electrode is over the dielectric structure and in contact with the second and third portions of the dielectric structure.

Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.

Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.

Abstract: A memory device includes a transistor and a memory cell. The memory cell includes a bottom electrode, a top electrode, and a dielectric structure. The top electrode is electrically connected to the transistor. The dielectric structure includes a thin portion and a thick portion. The thin portion is sandwiched between the bottom electrode and the top electrode. The thick portion is thicker than the thin portion and between the bottom electrode and the top electrode.

Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.

Abstract: A device includes a substrate, a first electrode and a second electrode. The first electrode is disposed on the substrate, and configured to receive an input signal. The second electrode is disposed on the substrate, and configured to output an output signal based on the input signal. When the input signal is configured to oscillate within a first range between a first voltage value and a second voltage value with a first frequency, the output signal is an inverted version of the input signal, and has the first frequency. When the input signal is configured to oscillate within a second range including the first voltage value without the second voltage value with the first frequency, the output signal has a second frequency which is approximately twice of the first frequency.

Abstract: A device is disclosed that includes an insulating layer, a first electrode, a second electrode, and a bottom electrode. The insulating layer is disposed on a first surface of a substrate. The first electrode and the second electrode are disposed on a first surface of the insulating layer. The first electrode receives an input signal, and the second electrode outputs, in response to the input signal, an output signal. The bottom electrode is disposed on a second surface, opposite to the first surface, of the substrate and receives an operating voltage to modify a frequency of the output signal.