Abstract: A bridging contact between internal contacts in a semiconductor integrated circuit is formed which is insulated from any connection to an intervening feature. A first dielectric layer is deposited over the contacts and the intervening feature, followed by an etch stop layer. The etch stop layer is patterned to form an etch stop mask and a second dielectric layer is deposited over the first dielectric layer and the patterned etch stop. The first and second dielectric layers are etched to form a trench opening and a pair of communicating passageways in the dielectric layers which expose the internal contacts. The etch stop mask protects and controls the vertical and horizontal dimensions of the resultant dielectric insulator that protects the intervening feature. Metal is deposited in the opening and passageways to form a bridging contact between the contacts. The bridging contact is electrically isolated from the intervening feature by the dielectric insulator remaining over and around the intervening feature.

Abstract: A bridging contact between internal contacts in a semiconductor integrated circuit is formed which is insulated from any connection to an intervening feature. A first dielectric layer is deposited over the contacts and the intevening feature, followed by an etch stop layer. The etch stop layer is patterned to form an etch stop mask and a second dielectric layer is deposited over the first dielectric layer and the patterned etch stop. The first and second dielectric layers are etched to form a trench opening and a pair of communicating passageways in the dielectric layers which expose the internal contacts. The etch stop mask protects and controls the vertical and horizontal dimensions of the resultant dielectric insulator that protects the intervening feature. Metal is deposited in the opening and passageways to form a bridging contact between the contacts. The bridging contact is electrically isolated from the intervening feature by the dielectric insulator remaining over and around the intervening feature.

Abstract: A self-assigned, self-planarized metallization scheme for multilevel interconnections using self-aligned windows in integrated circuits is described. Trenches are etched into a dielectric and then, using an etch stop layer on top of the dielectric to prevent unwanted etching of the dielectric, self-aligned windows which expose portions of the substrate are etched in the dielectric. Self-aligned windows can also be formed without a mask.