Patents by Inventor Jenn M. Huang

Jenn M. Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5607881
    Abstract: A new method of forming improved buried contact junctions is described. A buried contact is formed within a semiconductor substrate by dopant diffusion from an overlying polysilicon layer. The second polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein a portion of the buried contact within said semiconductor substrate is exposed. The polysilicon layer is overetched whereby a trench is etched into the exposed semiconductor substrate. An extra implant is implanted into the semiconductor substrate around the trench. Source and drain regions are formed wherein the buried contact connects to one of the source and drain regions through the extra implant around the trench completing the formation of the buried contact in the fabrication of an integrated circuit.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: March 4, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventor: Jenn M. Huang
  • Patent number: 5596215
    Abstract: A process for fabricating MOSFET devices, using an optimized buried contact approach, for source and drain contacts, has been developed. This process is forgiving for non-optimized photolithographic alignments, which when used as masks for dry etching, can result in the creation of trenches or crevices in the device region, ultimately degrading the conductive path from the buried contact region, to a polysilicon contact structure. Films used to create the spacer sidewalls on polysilicon gate structures, also fill the unwanted trench or crevice. Therefore materials are chosen, that have electrical charge characteristics of gate fringing field effects, that will result in the creation of a more conductive accumulation layer, for the contact path.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: January 21, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jenn M. Huang
  • Patent number: 5525552
    Abstract: A process for fabricating MOSFET devices, using an optimized buried contact approach, has been developed. The process includes the provision of thermal oxide (10) and polysilicon spacer (12) adjacent polysilicon buried contact (7) and gate (4). This process is forgiving for non-optimized photolithographic alignments, which when used as masks for dry etching, can result in the creation of trenches or crevices in the device region, to a polysilicon contact structure. Films used to create the spacer sidewalls on polysilicon gate structures, also fill the unwanted trench or crevice. Therefore materials, such as silicon nitride and tantalum oxide are chosen, that will result in the creation of a more conductive contact path, between the buried contact region and a polysilicon contact structure, due to the accumulation layer formed below these sidewall spacer materials.
    Type: Grant
    Filed: June 8, 1995
    Date of Patent: June 11, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jenn M. Huang